Intel SL22T Specifications download pdf (Page 11)

2-5

LOCAL X2APIC ARCHITECTURE

0120H 012H ISR bits 64:95 Read Only.

0130H 013H ISR bits 96:127 Read Only.

0140H 014H ISR bits 128:159 Read Only.

0150H 015H ISR bits 160:191 Read Only.

0160H 016H ISR bits 192:223 Read Only.

0170H 017H ISR bits 224:255 Read Only.

0180H 018H Trigger Mode Register

(TMR); bits 0:31

Read Only.

0190H 019H TMR bits 32:63 Read Only.

01A0H 01AH TMR bits 64:95 Read Only.

01B0H 01BH TMR bits 96:127 Read Only.

01C0H 01CH TMR bits 128:159 Read Only.

01D0H 01DH TMR bits 160:191 Read Only.

01E0H 01EH TMR bits 192:223 Read Only.

01F0H 01FH TMR bits 224:255 Read Only.

0200H 020H Interrupt Request

Read Only.

0210H 021H IRR bits32:63 Read Only.

0220H 022H IRR bits 64:95 Read Only.

0230H 023H IRR bits 96:127 Read Only.

0240H 024H IRR bits 128:159 Read Only.

0250H 025H IRR bits 160:191 Read Only.

0260H 026H IRR bits 192:223 Read Only.

0270H 027H IRR bits 224:255 Read Only.

0280H 028H Error Status Register Read/Write. GP fault on non-zero

writes

0290H-

02E0H

029H-02EH Reserved

02F0H 02FH Reserved

0300H-

0310H

030H

Interrupt Command

Read/Write.

Table 2-2. Local APIC Register Address Map Supported by x2APIC (Contd.)

MMIO Offset

(xAPIC mode)

MSR Offset

(x2APIC

mode) Register Name

R/W

Semantics Comments

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 34 35

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Intel SL22T Specifications Page 11

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