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Intel SL22T Specifications Page 30
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2-24
LO
C
A
L
X
2APIC ARCHITECTU
RE
•
R
e-directible/Lowest Priority inter-processor interrupts are not supported in
the
x2APIC architecture.
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Intel® 64 Architecture x2APIC
1
Specification
1
CHAPTER 1
3
INTRODUCTION
3
1.3 GLOSSARY
4
1.4 REFERENCES
5
• The ACPI 4.0 specification
5
CHAPTER 2
7
(xAPIC mode)
10
(x2APIC
11
2.3.3 Reserved Bit Checking
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2.3.4 Error Handling
13
2.3.5 MSR Access Semantics
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X2APIC ARCHITECTURE
14
MSR Address: 802H
17
MSR Address: 80DH
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Logical x2APIC ID
18
2.4.5 SELF IPI register
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ARCHITECTURE
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2.7.1 x2APIC States
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Disabled
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2.7.1.1 x2APIC After RESET
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2.9 SYSTEM TRANSITIONS
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LOCAL X2APIC ARCHITECTURE
30
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