Intel SL22T Specifications download pdf (Page 13)

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LOCAL X2APIC ARCHITECTURE

2.3.4 Error Handling

RDMSR and WRMSR operations to reserved addresses in the x2APIC mode will raise

a GP fault. (Note: In xAPIC mode, an APIC error is indicated in the Error Status

faults as detailed in Section 2.3.3. Beyond illegal register access and reserved bit

violations, other APIC errors are logged in Error Status Register. The details on Error

Status Register are in Section 2.3.5.4.

2.3.5 MSR Access Semantics

To allow for efficient access to the APIC registers in x2APIC mode, the serializing

semantics of WRMSR are relaxed when writing to the APIC registers. Thus, system

software should not use “WRMSR to APIC registers in x2APIC mode” as a serializing

instruction. Read and write accesses to the APIC registers will occur in program

order.

Additional semantics for the WRMSR instruction expected by system software for

specific registers (EOI, TPR, SELF IPI) are described in Section 2.3.5.3, Section

2.3.5.2, and Section 2.4.5.

The RDMSR instruction is not serializing and this behavior is unchanged when

reading APIC registers in x2APIC mode. System software accessing the APIC regis-

ters using the RDMSR instruction should not expect a serializing behavior. (Note: The

MMIO-based xAPIC interface is mapped by system software as an un-cached region.

Consequently, read/writes to the xAPIC-MMIO interface have serializing semantics in

the xAPIC mode.)

There are some simplifications to the means used by system software for accessing

the Interrupt Control Register via the register interface in the x2APIC mode. These

changes are described in Section 2.3.5.1.

2.3.5.1 Interrupt Command Register Semantics

A processor generates an inter-processor interrupt (IPI) by writing to the Interrupt

Command Register (ICR) in the local xAPIC unit. In xAPIC mode, ICR contains a

delivery status bit (bit 12) that indicates the status of the delivery of this interrupt.

The field has software read-only semantics. A value of 0 implies that there is

currently no activity while a value of 1 implies that the transmission is pending. The

delivery status bit gets cleared when the interrupt has been transmitted. With the

legacy xAPIC interface, system software would poll the delivery status bit until it is

clear prior to sending an IPI. Similarly if the semantics of the send operation required

that the interrupt be sent from the local xAPIC unit, then system software would

busy-wait for the delivery status bit to be cleared.

In the x2APIC mode, the semantics of programming Interrupt Command Register to

dispatch an interrupt is simplified. A single MSR write to the 64-bit ICR (see Figure 2-

5) is required for dispatching an interrupt.

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Intel SL22T Specifications Page 13