Intel LF80537GG0252M Datasheet download pdf (Page 97)

Datasheet 97

Package Mechanical Specifications and Pin Information

INIT# Input

INIT# (Initialization), when asserted, resets integer registers inside

the processor without affecting its internal caches or floating-point

registers. The processor then begins execution at the power-on

Reset vector configured during power-on configuration. The

processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure

recognition of this signal following an input/output write instruction,

it must be valid along with the TRDY# assertion of the

corresponding input/output write bus transaction. INIT# must

connect the appropriate pins of both FSB agents.

If INIT# is sampled active on the active-to-inactive transition of

RESET#, then the processor executes its Built-in Self-Test (BIST)

LINT[1:0] Input

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins

of all APIC Bus agents. When the APIC is disabled, the LINT0 signal

becomes INTR, a maskable interrupt request signal, and LINT1

becomes NMI, a nonmaskable interrupt. INTR and NMI are

backward-compatible with the signals of those names on the

Pentium processor. Both signals are asynchronous.

Both of these signals must be software configured via BIOS

programming of the APIC register space to be used either as NMI/

INTR or LINT[1:0]. Because the APIC is enabled by default after

Reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK#

Input/

Output

LOCK# indicates to the system that a transaction must occur

atomically. This signal must connect the appropriate pins of both

FSB agents. For a locked sequence of transactions, LOCK# is

asserted from the beginning of the first transaction to the end of

the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of

the FSB, it will wait until it observes LOCK# deasserted. This

enables symmetric agents to retain ownership of the FSB

throughout the bus locked operation and ensure the atomicity of

lock.

PRDY# Output

Probe Ready signal used by debug tools to determine processor

debug readiness.

PREQ# Input

Probe Request signal used by debug tools to request debug

operation of the processor.

PROCHOT#

Input/

Output

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the

processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit (TCC) has

been activated, if enabled. As an input, assertion of PROCHOT# by

the system will activate the TCC, if enabled. The TCC will remain

active until the system deasserts PROCHOT#.

By default PROCHOT# is configured as an output. The processor

must be enabled via the BIOS for PROCHOT# to be configured as

bidirectional.

This signal may require voltage translation on the motherboard.

PSI# Output

Processor Power Status Indicator signal. This signal is asserted

when the processor is both in the normal state (HFM to LFM) and in

lower power states (Deep Sleep and Deeper Sleep).

Table 19. Signal Description (Sheet 5 of 8)

Name Type Description

1 2 ... 92 93 94 95 96 97 98 99 100 101 102 ... 112 113

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Intel LF80537GG0252M Datasheet Page 97

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