Intel LF80537GG0252M Datasheet download pdf (Page 13)

Datasheet

Low Power Features

NOTE:

1. AutoHALT or MWAIT/C1.

2.1.1 Core Low-Power State Descriptions

2.1.1.1 Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2 Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when a core executes the HALT instruction.

The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,

LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to

immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures

Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more

information.

Figure 2. Package Low-Power States

Table 1. Coordination of Core Low-Power States at the Package Level

Package State Core1 State

Core0 State C0 C1

C2 C3

C4/Deep Power Down

Technology State

(Code Named C6 State)

C0 Normal Normal Normal Normal Normal

Normal Normal Normal Normal Normal

C2 Normal Normal Stop-Grant Stop-Grant Stop-Grant

C3 Normal Normal Stop-Grant Deep Sleep Deep Sleep

C4/Deep Power

Down Technology

Normal Normal Stop-Grant Deep Sleep

Deeper Sleep /Intel®

Enhanced Deeper Sleep/

Intel® Deep Power Down

Stop Grant

Snoop

Normal

Stop

Grant

Deep

Sleep

STPCLK# asserted

Snoop

serviced

Snoop

occurs

Deeper

Sleep

†

Sleep

SLP# asserted

SLP# deasserted

DPSLP# asserted

DPSLP# deasserted DPRSTP# deasserted

DPRSTP# asserted

STPCLK# deasserted

† — Deeper Sleep includes the Deeper Sleep state, Deep C4 sub-state, and C6

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