Intel LF80537GG0252M Datasheet Page 75
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Package Mechanical Specifications and Pin Information
Datasheet 75
C8 VSS Power/Other
C9 VCC Power/Other
C10 VCC Power/Other
C11 VSS Power/Other
C12 VCC Power/Other
C13 VCC Power/Other
C14 VSS Power/Other
C15 VCC Power/Other
C16 VSS Power/Other
C17 VCC Power/Other
C18 VCC Power/Other
C19 VSS Power/Other
C20 DBR# CMOS Output
C21 BSEL[2] CMOS Output
C22 VSS Power/Other
C23 TEST1 Test
C24 TEST3 Test
C25 VSS Power/Other
C26 VCCA Power/Other
D1 VSS Power/Other
D2 RSVD Reserved
D3 RSVD Reserved
D4 VSS Power/Other
D5 STPCLK# CMOS Input
D6 PWRGOOD CMOS Input
D7 SLP# CMOS Input
D8 VSS Power/Other
D9 VCC Power/Other
D10 VCC Power/Other
D11 VSS Power/Other
D12 VCC Power/Other
D13 VSS Power/Other
D14 VCC Power/Other
D15 VCC Power/Other
D16 VSS Power/Other
D17 VCC Power/Other
D18 VCC Power/Other
D19 VSS Power/Other
D20 IERR# Open Drain Output
Table 17. Pin # Listing
Pin # Pin Name
Signal Buffer
Type
Directi
on
D21
PROCHOT
#
Open Drain
Input/
Output
D22 RSVD Reserved
D23 VSS Power/Other
D24 DPWR# Common Clock
Input/
Output
D25 TEST2 Test
D26 VSS Power/Other
E1 DBSY# Common Clock
Input/
Output
E2 BNR# Common Clock
Input/
Output
E3 VSS Power/Other
E4 HITM# Common Clock
Input/
Output
E5 DPRSTP# CMOS Input
E6 VSS Power/Other
E7 VCC Power/Other
E8 VSS Power/Other
E9 VCC Power/Other
E10 VCC Power/Other
E11 VSS Power/Other
E12 VCC Power/Other
E13 VCC Power/Other
E14 VSS Power/Other
E15 VCC Power/Other
E16 VSS Power/Other
E17 VCC Power/Other
E18 VCC Power/Other
E19 VSS Power/Other
E20 VCC Power/Other
E21 VSS Power/Other
E22 D[0]# Source Synch
Input/
Output
E23 D[7]# Source Synch
Input/
Output
E24 VSS Power/Other
E25 D[6]# Source Synch
Input/
Output
E26 D[2]# Source Synch
Input/
Output
F1 BR0# Common Clock
Input/
Output
Table 17. Pin # Listing
Pin # Pin Name
Signal Buffer
Type
Directi
on
- Intel® Core™2 Duo Mobile 1
- 2 Datasheet 2
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- Revision History 6
- 1 Introduction 7
- 1.1 Terminology 8
- 1.2 References 9
- 2 Low Power Features 11
- Low Power Features 12
- 12 Datasheet 12
- 2.1.1.1 Core C0 State 13
- 2.1.1.4 Core C2 State 14
- 2.1.1.5 Core C3 State 14
- 2.1.1.6 Core C4 State 14
- 2.1.2.1 Normal State 15
- 2.1.2.2 Stop-Grant State 15
- 2.1.2.4 Sleep State 16
- 2.1.2.5 Deep Sleep State 16
- 2.1.2.6 Deeper Sleep State 17
- ® Enhanced Deeper Sleep State 17
- 18 Datasheet 18
- 2.3 Extended Low-Power States 20
- 2.5 VID-x 23
- 24 Datasheet 24
- 3 Electrical Specifications 25
- 3.5 Reserved and Unused Pins 29
- 3.7 FSB Signal Groups 30
- 3.8 CMOS Signals 31
- 3.9 Maximum Ratings 31
- Processors (Sheet 2 of 2) 33
- Processor 38
- (5.5 W) SFF Processor 41
- Figure 4. Active V 43
- 13mV= RIPPLE 44
- 10mV= RIPPLE 45
- Electrical Specifications 50
- 50 Datasheet 50
- 4 Package Mechanical 51
- Specifications and Pin 51
- Information 51
- 52 Datasheet 52
- Datasheet 53 53
- 54 Datasheet 54
- Datasheet 55 55
- 56 Datasheet 56
- Datasheet 57 57
- Processor Package Drawing 58
- Datasheet 59 59
- 60 Datasheet 60
- Table 16. Pin Name Listing 61
- Table 17. Pin # Listing 72
- 80 Datasheet 80
- Datasheet 81 81
- 82 Datasheet 82
- Datasheet 83 83
- 5 Thermal Specifications and 101
- Design Considerations 101
- SFF Processors 104
- Processors 107
- 5.1.1 Thermal Diode 108
- 5.1.2 Intel® Thermal Monitor 109
- 110 Datasheet 110
- 5.1.3 Digital Thermal Sensor 111
- 5.3 PROCHOT# Signal Pin 112
- Datasheet 113
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