Intel LF80537GG0252M Datasheet Page 37
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Datasheet
37
Electrical Specifications
NOTES:
1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
Table 9. Voltage and Current Specifications for the Dual-Core, Power Optimized
Performance (25 W) SFF Processors
Symbol Parameter Min Typ Max Unit Notes
V
CCDAM
V
CC
in Enhanced Intel® Dynamic Acceleration
Technology Mode
0.9 — 1.275 V 1, 2
V
CCHFM
V
CC
at Highest Frequency Mode (HFM) 0.9 — 1.2125 V 1, 2
V
CCLFM
V
CC
at Lowest Frequency Mode (LFM) 0.85 — 1.025 V 1, 2
V
CCSLFM
V
CC
at Super Low Frequency Mode (Super LFM) 0.75 — 0.95 V 1, 2
V
CC,BOOT
Default V
CC
Voltage for Initial Power Up — 1.20 — V 2, 6, 8
V
CCP
AGTL+ Termination Voltage 1.00 1.05 1.10 V
V
CCA
PLL Supply Voltage 1.425 1.5 1.575 V
V
CCDPRSLP
V
CC
at Deeper Sleep 0.65 — 0.85 V 1, 2
V
DC4
V
CC
at Intel® Enhanced Deeper Sleep State 0.6 — 0.85 V 1, 2
V
CCDPPWDN
V
CC
at Deep Power Down Technology State (C6) 0.35 — 0.7 V 1, 2
I
CCDES
I
CC
for Processors Recommended Design Target — — 37 A 5
I
CC
Processor
Number
Core Frequency/Voltage — — —
SP9600
SP9400
SP9300
2.53 GHz & V
CCHFM
2.4 GHz & V
CCHFM
2.26 GHz & V
CCHFM
1.2 GHz & V
CCLFM
0.8 GHz & V
CCSLFM
——
37
37
37
28
17
A 3, 4, 12
I
AH,
I
SGNT
I
CC
Auto-Halt & Stop-Grant
HFM
SuperLFM
——
14.8
8.8
A 3, 4, 12
I
SLP
I
CC
Sleep
HFM
SuperLFM
——14.2
8.6
A 3, 4, 12
I
DSLP
I
CC
Deep Sleep
HFM
SuperLFM
——12.5
8.1
A 3, 4, 12
I
DPRSLP
I
CC
Deeper Sleep — — 6.9 A 3, 4
I
DC4
I
CC
Intel Enhanced Deeper Sleep State — — 5.9 A 3, 4
I
DPWDN
I
CC
Deep Power Down Technology State (C6) — — 3.5 A 3, 4
dI
CC/DT
V
CC
Power Supply Current Slew Rate at Processor
Package Pin
——600mA/µs7, 9
I
CCA
I
CC
for V
CCA
Supply — — 130 mA
I
CCP
I
CC
for V
CCP
Supply before V
CC
Stable
I
CC
for V
CCP
Supply after V
CC
Stable
——
4.5
2.5
A
A
10
11
- Intel® Core™2 Duo Mobile 1
- 2 Datasheet 2
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- Revision History 6
- 1 Introduction 7
- 1.1 Terminology 8
- 1.2 References 9
- 2 Low Power Features 11
- Low Power Features 12
- 12 Datasheet 12
- 2.1.1.1 Core C0 State 13
- 2.1.1.4 Core C2 State 14
- 2.1.1.5 Core C3 State 14
- 2.1.1.6 Core C4 State 14
- 2.1.2.1 Normal State 15
- 2.1.2.2 Stop-Grant State 15
- 2.1.2.4 Sleep State 16
- 2.1.2.5 Deep Sleep State 16
- 2.1.2.6 Deeper Sleep State 17
- ® Enhanced Deeper Sleep State 17
- 18 Datasheet 18
- 2.3 Extended Low-Power States 20
- 2.5 VID-x 23
- 24 Datasheet 24
- 3 Electrical Specifications 25
- 3.5 Reserved and Unused Pins 29
- 3.7 FSB Signal Groups 30
- 3.8 CMOS Signals 31
- 3.9 Maximum Ratings 31
- Processors (Sheet 2 of 2) 33
- Processor 38
- (5.5 W) SFF Processor 41
- Figure 4. Active V 43
- 13mV= RIPPLE 44
- 10mV= RIPPLE 45
- Electrical Specifications 50
- 50 Datasheet 50
- 4 Package Mechanical 51
- Specifications and Pin 51
- Information 51
- 52 Datasheet 52
- Datasheet 53 53
- 54 Datasheet 54
- Datasheet 55 55
- 56 Datasheet 56
- Datasheet 57 57
- Processor Package Drawing 58
- Datasheet 59 59
- 60 Datasheet 60
- Table 16. Pin Name Listing 61
- Table 17. Pin # Listing 72
- 80 Datasheet 80
- Datasheet 81 81
- 82 Datasheet 82
- Datasheet 83 83
- 5 Thermal Specifications and 101
- Design Considerations 101
- SFF Processors 104
- Processors 107
- 5.1.1 Thermal Diode 108
- 5.1.2 Intel® Thermal Monitor 109
- 110 Datasheet 110
- 5.1.3 Digital Thermal Sensor 111
- 5.3 PROCHOT# Signal Pin 112
- Datasheet 113
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