Intel PXA26X User Manual

Intel® PXA26x Processor FamilyDeveloper’s ManualMarch, 2003Order Number: 278638-002

x Intel® PXA26x Processor Family Developer’s Manual Contents12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11...12-2612.

3-34 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.5.12 Power Manager Register LocationsTable 3-20 shows the registers

Intel® PXA26x Processor Family Developer’s Manual 3-35 Clocks and Power Manager3.6 Clocks Manager RegistersThe clocks manager contains three registers

3-36 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power ManagerTable 3-21. CCCR Register Bitmap and Bit Definitions 0x4130 0000Core C

Intel® PXA26x Processor Family Developer’s Manual 3-37 Clocks and Power Manager3.6.2 Clock Enable Register (CKEN)CKEN enables or disables the clocks t

3-38 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager8CKEN8I2S UNIT CLOCK ENABLE:0 – Clock to the unit is disabled1 – Clock

Intel® PXA26x Processor Family Developer’s Manual 3-39 Clocks and Power Manager3.6.3 Oscillator Configuration Register (OSCC)The OSCC, refer to Table

3-40 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.7 Coprocessor 14: Clock and Power ManagementCoprocessor 14 contains

Intel® PXA26x Processor Family Developer’s Manual 3-41 Clocks and Power Manager3.7.2 Power Mode Register (PWRMODE)Use the PWRMODE register (CP14, regi

3-42 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power ManagerA 3.6864-MHz crystal must be connected between the PXTAL and PEXTAL pi

Intel® PXA26x Processor Family Developer’s Manual 4-1System Integration Unit 4This chapter describes the System Integration Unit (SIU) for the Intel

Intel® PXA26x Processor Family Developer’s Manual xi Contents14.3.5 Receive FIFO Errors...

4-2 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitValidate each GPIO pin’s state by reading the GPIO Pin Level Register (GP

Intel® PXA26x Processor Family Developer’s Manual 4-3System Integration Unit4.1.2 GPIO Alternate FunctionsGPIO pins are capable of having as many as

4-4 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitGP28BITCLK ALT_FN_1_IN 01 AC97 Controller Unit AC97 bit_clkBITCLK ALT_FN_

Intel® PXA26x Processor Family Developer’s Manual 4-5System Integration UnitGP44BTCTS ALT_FN_1_IN 01 UARTs BTUART clear to sendHWCTS ALT_FN_3_IN 11

4-6 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitGP66LDD[8] ALT_FN_2_OUT 10 LCD Controller LCD data pin 8MBREQ ALT_FN_1_IN

Intel® PXA26x Processor Family Developer’s Manual 4-7System Integration Unit4.1.3 GPIO Register DefinitionsThere are a total of twenty-seven 32-bit

4-8 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitNote: GPLR2[31:26], GPSR2[31:26], GPCR2[31:26], GPDR2[31:26], GRER2[31:26

Intel® PXA26x Processor Family Developer’s Manual 4-9System Integration UnitThis is read/write register. Ignore reads from reserved bits. Write zero

4-10 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitTable 4-6. GPDR0 Bit DefinitionsPhysical Address0x40E0_000CGPDR0 System

Intel® PXA26x Processor Family Developer’s Manual 4-11System Integration Unit4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin

xii Intel® PXA26x Processor Family Developer’s Manual Contents15.5.5 MMC_CMDAT Register...

4-12 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitTable 4-11. GPSR2 Register BitmapPhysical Address0x40E0_0020GPIO Pin Out

Intel® PXA26x Processor Family Developer’s Manual 4-13System Integration Unit4.1.3.4 GPIO Rising Edge Detect Enable Registers (GRER0, GRER1, GRER2)

4-14 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitNote: For reserved bits in GRER2 and GFER2, writes must be zeros and rea

Intel® PXA26x Processor Family Developer’s Manual 4-15System Integration UnitTable 4-18. GFER0 Bit DefinitionsPhysical Address0x40E0_003CGFER0 Syste

4-16 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.1.3.5 GPIO Edge Detect Status Register (GEDR)The GPIO Edge Detect Stat

Intel® PXA26x Processor Family Developer’s Manual 4-17System Integration Unit4.1.3.6 GPIO Alternate Function Register (GAFR)The GPIO alternate funct

4-18 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit• “00” indicates normal GPIO function for GPIO[85:0]. Indicates default

Intel® PXA26x Processor Family Developer’s Manual 4-19System Integration UnitTable 4-26. GAFR1_L Bit DefinitionsPhysical Address0x40E0_005CGAFR1_L S

4-20 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitTable 4-28. GAFR2_L Bit DefinitionsPhysical Address0x40E0_0064GAFR2_L Sy

Intel® PXA26x Processor Family Developer’s Manual 4-21System Integration Unit4.1.3.7 Example Procedure for Configuring the Alternate Function Regist

Intel® PXA26x Processor Family Developer’s Manual xiii Contents17.5.4 Interrupt Enable Register (IER) ...

4-22 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.2 Interrupt ControllerThe Interrupt Controller controls the interrupt

Intel® PXA26x Processor Family Developer’s Manual 4-23System Integration Unit4.2.1 Interrupt Controller OperationThe Interrupt Controller provides m

4-24 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.2.2 Interrupt Controller Register DefinitionsThe interrupt controller

Intel® PXA26x Processor Family Developer’s Manual 4-25System Integration UnitTable 4-31 shows the bitmap of the Interrupt Controller Mask Register.

4-26 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.2.2.3 Interrupt Controller Control Register (ICCR)The Interrupt Contro

Intel® PXA26x Processor Family Developer’s Manual 4-27System Integration Unit4.2.2.5 Interrupt Controller Pending Register (ICPR)The ICPR is a 32-bi

4-28 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitTable 4-36. ICPR Register Bitmap (Sheet 1 of 3)Physical Address0x40D0_00

Intel® PXA26x Processor Family Developer’s Manual 4-29System Integration Unit<19> IS19ICP TRANSMIT/RECEIVE/ERROR INTERRUPT PENDING:0 – Interru

4-30 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit<8> IS8GPIO[0] Edge Detect Interrupt Pending0 – Interrupt NOT pend

Intel® PXA26x Processor Family Developer’s Manual 4-31System Integration UnitSeveral units have more than one source per interrupt signal. When an i

xiv Intel® PXA26x Processor Family Developer’s Manual Contents6-14 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0:RDF = 4, MSC0:RDN = 1,

4-32 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.3 Real-Time Clock (RTC)Use the RTC to configure a clock source with a

Intel® PXA26x Processor Family Developer’s Manual 4-33System Integration Unit4.3.2.1 Real-Time Clock Trim Register (RTTR)Program the RTTR to set the

4-34 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.3.2.3 Real-Time Clock Counter Register (RCNR)The RTC Counter Register

Intel® PXA26x Processor Family Developer’s Manual 4-35System Integration UnitThey are cleared by writing ones to the AL and HZ bits. The AL and HZ b

4-36 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.3.3.1 Oscillator Frequency CalibrationTo determine the value programme

Intel® PXA26x Processor Family Developer’s Manual 4-37System Integration Unit4.3.3.2.2 Trim Example #2 – Measured Value Has a Fractional ComponentTh

4-38 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitThe trim procedure can counteract these factors by providing a highly ac

Intel® PXA26x Processor Family Developer’s Manual 4-39System Integration Unit4.4.2 Operating System Timer Register Definitions4.4.2.1 Operating Syst

4-40 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.4.2.3 Operating System Timer Watchdog Match Enable Register (OWER)The

Intel® PXA26x Processor Family Developer’s Manual 4-41System Integration Unit4.4.2.4 Operating System Timer Count Register (OSCR)The OS Timer Count

Intel® PXA26x Processor Family Developer’s Manual xv Contents9-5 Acknowledge on the I2C Bus...

4-42 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.4.3 Operating System Timer Register LocationsTable 4-49 shows the regi

Intel® PXA26x Processor Family Developer’s Manual 4-43System Integration Unit4.5 Pulse Width ModulatorUse the Pulse Width Modulator (PWM) to generat

4-44 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit4.5.1.1 InterdependenciesThe PWM unit is clocked off the 3.6864-MHz osci

Intel® PXA26x Processor Family Developer’s Manual 4-45System Integration Unit4.5.2.1 PWM Control Registers (PWM_CTRLn)The PWMn Control Register, PWM

4-46 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitThe FDCYCLE bit determines whether or not PWM_OUTn is a function of the

Intel® PXA26x Processor Family Developer’s Manual 4-47System Integration UnitNote: Due to internal timing requirements, all changes to any of the PW

4-48 Intel® PXA26x Processor Family Developer’s Manual System Integration UnitThe output waveform in Figure 4-4 is created by writing PWM_PERVALn[PV]

Intel® PXA26x Processor Family Developer’s Manual 4-49System Integration Unit

4-50 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit

Intel® PXA26x Processor Family Developer’s Manual 5-1Direct Memory Access Controller 5This chapter describes the on-chip direct memory access (DMA)

xvi Intel® PXA26x Processor Family Developer’s Manual Contents16-10 Programmable Serial Protocol (single transfers)...

5-2 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access ControllerFigure 5-1. DMAC Block Diagram5.1.1 Direct Memory Access Controll

Intel® PXA26x Processor Family Developer’s Manual 5-3Direct Memory Access ControllerChannel information must be maintained on a per-channel basis an

5-4 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access ControllerThe PREQ[37:0] bits are the active high internal signals from the

Intel® PXA26x Processor Family Developer’s Manual 5-5Direct Memory Access Controller• Set zero• Set threeThe pattern repeats for the next eight chan

5-6 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller5.1.4 Direct Memory Access DescriptorsThe DMAC operates in two di

Intel® PXA26x Processor Family Developer’s Manual 5-7Direct Memory Access ControllerFigure 5-3. No-Descriptor Fetch Mode Channel State5.1.4.2 Descri

5-8 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller— Word [3] -> DCMDx register for the current transfer. 6. The

Intel® PXA26x Processor Family Developer’s Manual 5-9Direct Memory Access Controller5.1.4.3 Servicing an InterruptIf software receives an interrupt

5-10 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller5.1.7 Byte Transfer OrderThe DCMD[ENDIAN] bit indicates the byte

Intel® PXA26x Processor Family Developer’s Manual 5-11Direct Memory Access Controller5.1.8 Trailing BytesThe DMAC normally transfers bytes equal to

Intel® PXA26x Processor Family Developer’s Manual xvii Contents3-26 CCLKCFG Bit Definitions...

5-12 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller5.2.1 Servicing Internal PeripheralsThe DMAC provides the DMA Re

Intel® PXA26x Processor Family Developer’s Manual 5-13Direct Memory Access Controller1. The DMAC transfers the required number of bytes from the I/O

5-14 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller5.2.3 Servicing Companion Chips and External PeripheralsCompanio

Intel® PXA26x Processor Family Developer’s Manual 5-15Direct Memory Access ControllerDREQ[1:0]. The DREQ signal can be mapped to one of the 16 avail

5-16 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller3. At the end of the transfer, DTADRx is increased by the smalle

Intel® PXA26x Processor Family Developer’s Manual 5-17Direct Memory Access Controller• DCMD[INCSRCADDR] = 1• DCMD[INCTRGADDR] = 1• DCMD[FLOWSRC] = 0

5-18 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access ControllerTable 5-7. DMA Channel Control/Status Register Bitmap and Bit De

Intel® PXA26x Processor Family Developer’s Manual 5-19Direct Memory Access Controller5.3.3 DMA Request to Channel Map RegistersThe read/write DMA Re

5-20 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller5.3.4 DMA Descriptor Address RegistersThe DMA Descriptor Address

Intel® PXA26x Processor Family Developer’s Manual 5-21Direct Memory Access Controller 5.3.5 DMA Source Address RegistersThe DMA Source Address Regis

xviii Intel® PXA26x Processor Family Developer’s Manual Contents4-49 OS Timer Register Locations ...

5-22 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller5.3.6 DMA Target Address RegistersTo software, the DMA Target Ad

Intel® PXA26x Processor Family Developer’s Manual 5-23Direct Memory Access Controller5.3.7 DMA Command RegistersFor software, the DMA Command Regist

5-24 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access ControllerTable 5-12. DCMDx Register Bitmap and Bit Definitions (Sheet 1 o

Intel® PXA26x Processor Family Developer’s Manual 5-25Direct Memory Access Controller5.4 ExamplesThis section contains examples that show how to:• S

5-26 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access ControllerExample 5-1. How to set up and start a channel:The following exa

Intel® PXA26x Processor Family Developer’s Manual 5-27Direct Memory Access Controller7. Program the channel’s DDADR with the descriptor created in S

5-28 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller5.5 Direct Memory Access Controller Registers LocationsThis sect

Intel® PXA26x Processor Family Developer’s Manual 5-29Direct Memory Access Controller0x4000 0124 DRCMR9Request to Channel Map Register for AC97 mode

5-30 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller0x4000 0188 DRCMR34Request to Channel Map Register for HWUART tr

Intel® PXA26x Processor Family Developer’s Manual 5-31Direct Memory Access Controller0x4000 0270 DDADR7 DMA Descriptor Address Register channel 70x4

Intel® PXA26x Processor Family Developer’s Manual xix Contents6-33 Common Memory Space Read Commands...

5-32 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller

Intel® PXA26x Processor Family Developer’s Manual 6-1Memory Controller 6This chapter describes the external memory interface structures and memory-r

6-2 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-1. General Memory Interface Configuration6.2 Functional DescriptionThe

Intel® PXA26x Processor Family Developer’s Manual 6-3Memory Controllerpartition pairs: the 0/1 pair and the 2/3 pair. The partitions in a pair must

6-4 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerThe VLIO interface differs from SRAM in that it allows the data-ready input sig

Intel® PXA26x Processor Family Developer’s Manual 6-5Memory ControllerFigure 6-2. SDRAM Memory System ExampleFigure 6-3 shows an alternate memory co

6-6 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-3. Asynchronous Static Memory System Example6.4 Memory AccessesIf a me

Intel® PXA26x Processor Family Developer’s Manual 6-7Memory ControllerTable 6-1 lists all the transactions that the processor can generate. No burst

6-8 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerIf memory does not occupy all 64 MB of the partition, reads and writes from or

Intel® PXA26x Processor Family Developer’s Manual 6-9Memory Controller6.6 Synchronous DRAM Memory InterfaceEach possible SDRAM portion of the Memory

ii Intel® PXA26x Processor Family Developer’s Manual ContentsINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE,

xx Intel® PXA26x Processor Family Developer’s Manual Contents10-6 Divisor Latch High Register – DLH...

6-10 Intel® PXA26x Processor Family Developer’s Manual Memory Controller22:21 DRAC2[1:0]SDRAM ROW ADDRESS BIT COUNT FOR PARTITION PAIR 2/3:00 – 11 row

Intel® PXA26x Processor Family Developer’s Manual 6-11Memory Controller9:8 DTC0[1:0]TIMING CATEGORY FOR SDRAM PAIR 0/1:00 – tRP = 2 clks, CL = 2, tR

6-12 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.6.2 SDRAM Mode Register Set Configuration RegisterThe MDMRS register issues

Intel® PXA26x Processor Family Developer’s Manual 6-13Memory Controller6.6.2.1 Low-Power SDRAM Mode Register Set Configuration RegisterUse the Low-P

6-14 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.6.3 SDRAM MDREFR RegisterMDREFR is a read/write register and contains contro

Intel® PXA26x Processor Family Developer’s Manual 6-15Memory ControllerRefer to Table 6-6.Table 6-6. MDREFR Register Bitmap (Sheet 1 of 3)4800 0004

6-16 Intel® PXA26x Processor Family Developer’s Manual Memory Controller19 K2DB2SDRAM CLOCK PIN 2 (SDCLK2) DIVIDE BY 2 CONTROL/STATUS:0 – SDCLK2 is sa

Intel® PXA26x Processor Family Developer’s Manual 6-17Memory Controller6.6.4 SDRAM Memory OptionsThe Dynamic Memory interface supports up to four pa

6-18 Intel® PXA26x Processor Family Developer’s Manual Memory Controller• SDRAM timing category • Data-bus width • Number of row, column, and bank add

Intel® PXA26x Processor Family Developer’s Manual 6-19Memory ControllerTable 6-4 shows how the SDRAM row and column addresses are mapped to the inte

Intel® PXA26x Processor Family Developer’s Manual xxi Contents12-27 UDC Endpoint x Data Register, Where x is 1, 6, or 11...

6-20 Intel® PXA26x Processor Family Developer’s Manual Memory Controller1x13x8x16 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 ‘0’ 8 7 6 5 4 3 2 11x13x

Intel® PXA26x Processor Family Developer’s Manual 6-21Memory ControllerTable 6-9. External to Internal Address Mapping for SA-1111 Addressing (Sheet

6-22 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerUse the information below to connect the processor to the SDRAM devices. Some

Intel® PXA26x Processor Family Developer’s Manual 6-23Memory Controller1x12x9x16 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A01x12x10x32 BA0 A11 A10 A9

6-24 Intel® PXA26x Processor Family Developer’s Manual Memory Controller2x13x10x16BA1BA0A12A11A10A9A8A7A6A5A4A3A2A1A02x13x11x32 NOT VALID (too big)2x1

Intel® PXA26x Processor Family Developer’s Manual 6-25Memory Controller6.6.5 SDRAM Command OverviewThe processor accesses SDRAM with the following s

6-26 Intel® PXA26x Processor Family Developer’s Manual Memory Controller• Power-Down (PWRDN)• Enter Self-Refresh (SLFRSH)• Exit Power-Down (PWRDNX)• N

Intel® PXA26x Processor Family Developer’s Manual 6-27Memory Controller6.6.6 SDRAM WaveformsAdditional waveforms for the SDRAM controller are shown

6-28 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-7. SDRAM Read With a Second Read to Same Bank, Different RowFigure 6-

Intel® PXA26x Processor Family Developer’s Manual 6-29Memory Controller Figure 6-9. SDRAM WriteFigure 6-10. SDRAM Write With a Second Write to Same

xxii Intel® PXA26x Processor Family Developer’s Manual Contents15-9 MMC_SPI Register...

6-30 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.7 Synchronous Static Memory InterfaceThe synchronous static memory interface

Intel® PXA26x Processor Family Developer’s Manual 6-31Memory Controller25:24 SXRA2SX MEMORY ROW ADDRESS BIT COUNT FOR PARTITION PAIR 2/3:00 – 12 row

6-32 Intel® PXA26x Processor Family Developer’s Manual Memory Controller20:18 SXCL2CAS LATENCY FOR SX MEMORY PARTITION PAIR 2/3:Number of external SDC

Intel® PXA26x Processor Family Developer’s Manual 6-33Memory Controller11:10 SXCA0SX MEMORY COLUMN ADDRESS BIT COUNT FOR PARTITION PAIR 0/1:00 – 7 c

6-34 Intel® PXA26x Processor Family Developer’s Manual Memory Controller7:5 SXRL0RAS LATENCY FOR SYNCHRONOUS STATIC (SX) MEMORY PARTITION PAIR 0/1:Num

Intel® PXA26x Processor Family Developer’s Manual 6-35Memory Controller6.7.1.1 SMROM Memory OptionsTable 6-16 shows the possible external-to-interna

6-36 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.7.2 Synchronous Static Memory Mode Register Set Configuration RegisterOn pow

Intel® PXA26x Processor Family Developer’s Manual 6-37Memory Controller6.7.3 Synchronous Static Memory Timing DiagramsA three-beat read cycle for SM

6-38 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-11. SMROM Read Timing Diagram Half-Memory Clock Frequency, 6.7.4 Non-

Intel® PXA26x Processor Family Developer’s Manual 6-39Memory ControllerTable 6-19 shows sample frequency configurations for programming non-SDRAM ti

Intel® PXA26x Processor Family Developer’s Manual xxiii ContentsRevision HistoryDate Revision DescriptionOctober 2002 Public Release -001 Released to

6-40 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.7.4.1 Non-SDRAM Timing Flash Read Timing DiagramThe burst-of-eight read timi

Intel® PXA26x Processor Family Developer’s Manual 6-41Memory Controller• nADV assert time = 3 MEMCLKs• MA, nCS setup to nADV asserted = 1 MEMCLK• nA

6-42 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerThe RT fields in the MSCx registers specify the type of memory: • Non-burst RO

Intel® PXA26x Processor Family Developer’s Manual 6-43Memory ControllerTable 6-22. 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0]DQM[3

6-44 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.8.2 Asynchronous Static Memory Control Registers (MSC0 – 2)The MSC0, MSC1, a

Intel® PXA26x Processor Family Developer’s Manual 6-45Memory ControllerTable 6-25. MSC0/1/2 Register Bit Definitions (Sheet 1 of 3)0X4800 0008/0x480

6-46 Intel® PXA26x Processor Family Developer’s Manual Memory Controller7:4 Read/Write RDFx<3:0>ROM DELAY FIRST ACCESS:RDF programmed RDF value

Intel® PXA26x Processor Family Developer’s Manual 6-47Memory ControllerTable 6-26 provides a comparison of supported Asynchronous Static Memory type

6-48 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.8.3 ROM InterfaceThe processor provides programmable timing for both burst a

Intel® PXA26x Processor Family Developer’s Manual 6-49Memory ControllerFigure 6-14. 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0:RDF

xxiv Intel® PXA26x Processor Family Developer’s Manual Contents

6-50 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-15. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash (MSC

Intel® PXA26x Processor Family Developer’s Manual 6-51Memory Controller6.8.4 SRAM Interface OverviewThe processor provides a 16-bit or 32-bit asynch

6-52 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFor writes to SRAM, if all byte enables are turned off (masking out the data,

Intel® PXA26x Processor Family Developer’s Manual 6-53Memory Controller• tAH = Address hold after nWE deasserted = 1 MEMCLK• nWE high time between b

6-54 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-18. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait

Intel® PXA26x Processor Family Developer’s Manual 6-55Memory ControllerFigure 6-19. 32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variabl

6-56 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.8.6 FLASH Memory InterfaceThe processor provides an SRAM-like interface for

Intel® PXA26x Processor Family Developer’s Manual 6-57Memory ControllerFigure 6-20. Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes)In Figu

6-58 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.9.1 Expansion Memory Timing Configuration RegisterMCMEM0, MCMEM1, MCATT0, MC

Intel® PXA26x Processor Family Developer’s Manual 6-59Memory Controller:13:12 — Reserved11:7MCATTx_ASSTCode for the command assertion time – See Tab

Intel® PXA26x Processor Family Developer’s Manual 1-1Introduction 1The Intel® PXA26x Processor Family is a 32-bit, multi-chip device which combines

6-60 Intel® PXA26x Processor Family Developer’s Manual Memory Controller00101 5 7 13 14 20 2100110 6 8 15 16 23 2400111 7 9 17 18 26 2701000 8 10 19 2

Intel® PXA26x Processor Family Developer’s Manual 6-61Memory Controller6.9.2 Expansion Memory Configuration Register (MECR)To eliminate external har

6-62 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-24. 16-Bit PC Card Memory MapThe 16-bit PC Card Memory Map space is d

Intel® PXA26x Processor Family Developer’s Manual 6-63Memory Controller Table 6-32. Common Memory Space Write CommandsnPCE2 nPCE1 MA<0> nPOE

6-64 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.9.4 External Logic for 16-Bit PC Card ImplementationThe PXA26x processor fa

Intel® PXA26x Processor Family Developer’s Manual 6-65Memory ControllerFigure 6-25. Expansion Card External Logic for a One-Socket ConfigurationFigu

6-66 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-26. Expansion Card External Logic for a Two-Socket ConfigurationD(15:

Intel® PXA26x Processor Family Developer’s Manual 6-67Memory Controller6.9.5 Expansion Card Interface Timing Diagrams and ParametersFigure 6-27 show

6-68 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-28. 16-Bit PC Card I/O 16-Bit Access to 8-Bit DeviceThe interface wai

Intel® PXA26x Processor Family Developer’s Manual 6-69Memory ControllerFigure 6-29. Alternate Bus Master ModeFigure 6-30. Variable Latency IOPXA26x

1-2 Intel® PXA26x Processor Family Developer’s Manual Introduction1.2 System Integration FeaturesThe PXA26x processor family features are:• Integrated

6-70 Intel® PXA26x Processor Family Developer’s Manual Memory Controller6.10.1 Alternate Bus Master ModeThe processor supports the presence of an alte

Intel® PXA26x Processor Family Developer’s Manual 6-71Memory Controller7. The memory controller performs an SDRAM refresh if SDRAM clocks and clock

6-72 Intel® PXA26x Processor Family Developer’s Manual Memory Controlleris deasserted or, as part of the sleep entry routine, the alternate master can

Intel® PXA26x Processor Family Developer’s Manual 6-73Memory Controller6.11.2.2 Boot-Time ConfigurationsThe boot time configurations are shown in Fi

6-74 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerFigure 6-32. SMROM Boot Time Configurations and Register DefaultsBOOT_SEL[2:0]

Intel® PXA26x Processor Family Developer’s Manual 6-75Memory ControllerFigure 6-33. SMROM Boot Time Configurations and Register Defaults (Continued)

6-76 Intel® PXA26x Processor Family Developer’s Manual Memory ControllerIn sleep mode, the memory pins and controller are in the same state as they ar

Intel® PXA26x Processor Family Developer’s Manual 6-77Memory Controllerbeing configured, the SDRAM banks must be disabled and MDREFR:APD must be dea

6-78 Intel® PXA26x Processor Family Developer’s Manual Memory Controller11. Optionally, in systems that contain SDRAM or synchronous static memory, en

Intel® PXA26x Processor Family Developer’s Manual 7-1Liquid Crystal Display Controller 7The liquid crystal display (LCD) controller provides an inte

Intel® PXA26x Processor Family Developer’s Manual 1-3IntroductionThe 3.6864-MHz crystal drives a core phase locked loop (PLL) and a peripheral PLL.

7-2 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controllerfrom the dither logic is grouped into the selected format (e.g.

Intel® PXA26x Processor Family Developer’s Manual 7-3Liquid Crystal Display ControllerFigure 7-1. LCD Controller Block DiagramLCD DMA ControllerRegi

7-4 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.1.2 Pin DescriptionsWhen the LCD controller is enabled, all o

Intel® PXA26x Processor Family Developer’s Manual 7-5Liquid Crystal Display Controller• Program all of the LCD configuration registers except the Fr

7-6 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller• Section 7.3.3, “Temporal Modulated Energy Distribution (TMED)

Intel® PXA26x Processor Family Developer’s Manual 7-7Liquid Crystal Display ControllerFigure 7-2. Temporal Dithering Concept - Single ColorThis dith

7-8 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller1. The new CV is sent through the color offset adjuster, where

Intel® PXA26x Processor Family Developer’s Manual 7-9Liquid Crystal Display Controller7.3.4 Output FIFOsThe LCD controller has two output FIFOs to q

7-10 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.3.5.2 Active-Display TimingIn active display mode (LCCR0[PAS

Intel® PXA26x Processor Family Developer’s Manual 7-11Liquid Crystal Display Controller7.4 Liquid Crystal Display External Palette and Frame Buffers

1-4 Intel® PXA26x Processor Family Developer’s Manual Introduction1.2.8 Multimedia Card (MMC) ControllerThe MMC controller provides a serial interface

7-12 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.4.2 External-Frame BufferThe external frame buffer is an off

Intel® PXA26x Processor Family Developer’s Manual 7-13Liquid Crystal Display Controller)Bit31302928... 3 2 1 0Base +0x0Pixel 31 Pixel 30 Pixel 29 Pi

7-14 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display ControllerNote: For passive 16 bits per pixel operation, the Raw Pixel D

Intel® PXA26x Processor Family Developer’s Manual 7-15Liquid Crystal Display ControllerIf dummy pixels are to be inserted, the panel must ignore the

7-16 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display ControllerFigure 7-12. Passive Mode Start-of-Frame TimingLine 0 Data Lin

Intel® PXA26x Processor Family Developer’s Manual 7-17Liquid Crystal Display ControllerFigure 7-13. Passive Mode End-of-Frame TimingFigure 7-14. Pas

7-18 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display ControllerFigure 7-15. Active Mode TimingLine 0 Data Line 1 Data Line 2

Intel® PXA26x Processor Family Developer’s Manual 7-19Liquid Crystal Display Controller7.6 Liquid Crystal Display Register DescriptionsThe LCD contr

7-20 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display ControllerAn additional control field exists to tune the DMAC’s performa

Intel® PXA26x Processor Family Developer’s Manual 7-21Liquid Crystal Display Controller19:12 PDDPALETTE DMA REQUEST DELAY (Section 7.6.1.3):Value (0

Intel® PXA26x Processor Family Developer’s Manual 1-5IntroductionThe STUART’s transmit and receive pins are multiplexed with the fast infrared commu

7-22 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.1.1 LCD Output Fifo Underrun Mask (OUM)The output FIFO und

Intel® PXA26x Processor Family Developer’s Manual 7-23Liquid Crystal Display ControllerAfter a word of palette data is written to the input FIFO, th

7-24 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display ControllerWhen PAS=1, active mode is selected. 1- and 2-bit pixel modes

Intel® PXA26x Processor Family Developer’s Manual 7-25Liquid Crystal Display Controller7.6.1.8 End of Frame Mask (EFM)The end of frame mask (EFM) bi

7-26 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.1.12 Single-/Dual-Panel Select (SDS)In passive mode (PAS=0

Intel® PXA26x Processor Family Developer’s Manual 7-27Liquid Crystal Display Controller7.6.1.13 Color/Monochrome Select (CMS)The color/monochrome se

7-28 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controllerblue pixel components. When CMS=1, monochrome mode is selected

Intel® PXA26x Processor Family Developer’s Manual 7-29Liquid Crystal Display Controller7.6.2.1 Beginning-of-Line Pixel Clock Wait Count (BLW)The 8-b

7-30 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controllerelapsed. When L_LCLK is asserted, the value in HSW is transfer

Intel® PXA26x Processor Family Developer’s Manual 7-31Liquid Crystal Display Controller7.6.3.1 Beginning-of-Frame Line Clock Wait Count (BFW)In acti

Intel® PXA26x Processor Family Developer’s Manual iii ContentsContents1 Introduction...

1-6 Intel® PXA26x Processor Family Developer’s Manual Introduction1.2.20 Network Synchronous Serial Protocol PortThe PXA26x processor family has an SS

7-32 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display ControllerAfter the count has elapsed, the VSYNC (L_FCLK) signal is puls

Intel® PXA26x Processor Family Developer’s Manual 7-33Liquid Crystal Display Controller7.6.3.4 Lines Per Panel (LPP)The lines per panel (LPP) bit fi

7-34 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.4.1 Double Pixel Clock (DPC)DPC doubles the rate of the pi

Intel® PXA26x Processor Family Developer’s Manual 7-35Liquid Crystal Display Controller0b100 = 16-bit pixels0b101–0b111 = reserved 7.6.4.3 Output En

7-36 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.4.7 AC Bias Pin Transitions Per Interrupt (API)The 4-bit A

Intel® PXA26x Processor Family Developer’s Manual 7-37Liquid Crystal Display Controller• Number of panels (single or dual)• Display type (monochrome

7-38 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.5.1 Frame DescriptorsAlthough the FDADRx registers are loa

Intel® PXA26x Processor Family Developer’s Manual 7-39Liquid Crystal Display Controllermemory location at the beginning of the palette data. The siz

7-40 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.5.5 LCD DMA Command Registers (LDCMDx)Registers LDCMD0 and

Intel® PXA26x Processor Family Developer’s Manual 7-41Liquid Crystal Display ControllerSoftware must load the palette at least once after enabling t

Intel® PXA26x Processor Family Developer’s Manual 2-1System Architecture 22.1 OverviewThe Intel® PXA26x Processor Family is an integrated system-on-

7-42 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display ControllerNote: In dual-panel mode, write to both FBR0 and FBR1 in order

Intel® PXA26x Processor Family Developer’s Manual 7-43Liquid Crystal Display ControllerTable 7-12. LCD Controller Status Register (Sheet 1 of 2)Phys

7-44 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.7.1 Subsequent Interrupt Status (SINT)SINT status is set w

Intel® PXA26x Processor Family Developer’s Manual 7-45Liquid Crystal Display Controller7.6.7.4 LCD Quick Disable Status (QD)QD is set when LCD enabl

7-46 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.7.10 Start Of Frame Status (SOF)SOF status is set after th

Intel® PXA26x Processor Family Developer’s Manual 7-47Liquid Crystal Display Controller(DSTN) displays. The default, recommended setting is 0x00AA55

7-48 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller7.6.10.1 TMED Energy Distribution Select (TED)TED selects whic

Intel® PXA26x Processor Family Developer’s Manual 7-49Liquid Crystal Display Controller7.6.10.4 TMED Frame Number Adjuster Enable (FNAME)The frame n

7-50 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller0x4400 020C LDCMD0 DMA channel 0 command register0x4400 0210 F

Intel® PXA26x Processor Family Developer’s Manual 8-1Synchronous Serial Port Controller 8This chapter describes the Synchronous Serial Port Controll

2-2 Intel® PXA26x Processor Family Developer’s Manual System Architecture2.2 Package TypesThe PXA26x processor family is available in a 13x13mm 294-pi

8-2 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port ControllerSSPEXTCLK is an external clock (input through GPIO27) that rep

Intel® PXA26x Processor Family Developer’s Manual 8-3Synchronous Serial Port Controller• SSPRXD – Receive signal for inbound data, from peripheral t

8-4 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller.8.4.1.2 SPI Format DetailsThe SPI format has four sub-modes.

Intel® PXA26x Processor Family Developer’s Manual 8-5Synchronous Serial Port ControllerFigure 8-2 shows one of the four configurations for the Motor

8-6 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port ControllerFigure 8-3 shows the National Microwire frame format with 8-bi

Intel® PXA26x Processor Family Developer’s Manual 8-7Synchronous Serial Port Controller8.5.1 Using Programmed I/O Data TransfersData words are 32 bi

8-8 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller“fullness” threshold that triggers an interrupt. Write to thes

Intel® PXA26x Processor Family Developer’s Manual 8-9Synchronous Serial Port Controller8.7.1.1 Data Size Select (DSS)The 4-bit data size select (DSS

8-10 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port ControllerThe transmit logic in the SSPC left-justifies the data sample

Intel® PXA26x Processor Family Developer’s Manual 8-11Synchronous Serial Port Controller8.7.1.5 Serial Clock Rate (SCR)Use the 8-bit serial clock ra

Intel® PXA26x Processor Family Developer’s Manual 2-3System Architecture2.3 Intel® XScale™ Microarchitecture Implementation OptionsThe processor inc

8-12 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller8.7.2.1 Receive FIFO Interrupt Enable (RIE)Use the Receive FI

Intel® PXA26x Processor Family Developer’s Manual 8-13Synchronous Serial Port ControllerNote: Loop back mode cannot be used with Microwire frame for

8-14 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller8.7.2.6 Microwire Transmit Data Size (MWDS)Use the Microwire

Intel® PXA26x Processor Family Developer’s Manual 8-15Synchronous Serial Port Controller8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT)This 4-bit

8-16 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port ControllerNote: Both FIFOs are cleared when the SSPC is reset or a zero

Intel® PXA26x Processor Family Developer’s Manual 8-17Synchronous Serial Port Controller8.7.4.1 Transmit FIFO Not Full Flag (TNF) (read-only, non-in

8-18 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller8.7.4.2 Receive FIFO Not Empty Flag (RNE) (read-only, non-int

Intel® PXA26x Processor Family Developer’s Manual 8-19Synchronous Serial Port Controller8.7.4.7 Transmit FIFO LevelThe 4-bit Transmit FIFO Level bit

8-20 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller

Intel® PXA26x Processor Family Developer’s Manual 9-1Inter-Integrated Circuit Bus Interface Unit 9This chapter describes the Inter-Integrated Circui

2-4 Intel® PXA26x Processor Family Developer’s Manual System Architecture2.3.3 Coprocessor 14 Register 6 and 7– Clock and Power ManagementThese regist

9-2 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface UnitFor example, when the processor I2C unit acts as a ma

Intel® PXA26x Processor Family Developer’s Manual 9-3Inter-Integrated Circuit Bus Interface Unit9.3.1 Operational BlocksThe I2C unit is connected to

9-4 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface UnitWhile the I2C unit is idle, it defaults to slave-rece

Intel® PXA26x Processor Family Developer’s Manual 9-5Inter-Integrated Circuit Bus Interface UnitFigure 9-2 shows the relationship between the SDA an

9-6 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit9.3.3.2 No START or STOP ConditionUse the no START or

Intel® PXA26x Processor Family Developer’s Manual 9-7Inter-Integrated Circuit Bus Interface Unit8. Repeated START (Repeat Step 1) or STOP9.4.1 Seria

9-8 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface UnitThe first byte transmission must be followed by an AC

Intel® PXA26x Processor Family Developer’s Manual 9-9Inter-Integrated Circuit Bus Interface UnitIn master-transmit mode, if the target slave-receive

9-10 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit9.4.4.2 SDA ArbitrationArbitration on the SDA line c

Intel® PXA26x Processor Family Developer’s Manual 9-11Inter-Integrated Circuit Bus Interface UnitIf the I2C unit loses arbitration as the address bi

Intel® PXA26x Processor Family Developer’s Manual 2-5System Architecture2.3.5 Coprocessor 15 Register 1 – P-BitBit 1 of this register is defined as

9-12 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface UnitTable 9-5. Master Transactions (Sheet 1 of 2)I2C Mas

Intel® PXA26x Processor Family Developer’s Manual 9-13Inter-Integrated Circuit Bus Interface UnitWhen the CPU needs to read data, the I2C unit trans

9-14 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit. \Figure 9-8. Master-Receiver Read from Slave-Tran

Intel® PXA26x Processor Family Developer’s Manual 9-15Inter-Integrated Circuit Bus Interface Unit9.4.6 Slave OperationsTable 9-6 describes how the I

9-16 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface UnitFigure 9-11 through Figure 9-13 are examples of I2C

Intel® PXA26x Processor Family Developer’s Manual 9-17Inter-Integrated Circuit Bus Interface Unitmaster-transmitter. Figure 9-14 shows a general cal

9-18 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit9.5 Slave Mode Programming ExamplesThe following sub

Intel® PXA26x Processor Family Developer’s Manual 9-19Inter-Integrated Circuit Bus Interface Unit9.5.3 Read n Bytes as a SlaveTo read n bytes as a s

9-20 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit5. Write a 1 to the ISR[ALD] bit if set.If the maste

Intel® PXA26x Processor Family Developer’s Manual 9-21Inter-Integrated Circuit Bus Interface Unit7. When an IDBR transmit empty interrupt occurs.Rea

2-6 Intel® PXA26x Processor Family Developer’s Manual System ArchitectureLoads and stores to internal addresses are generally completed more quickly t

9-22 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit13. Read IDBR data.14. Initiate STOP abort condition

Intel® PXA26x Processor Family Developer’s Manual 9-23Inter-Integrated Circuit Bus Interface Unit9.9.2 I2C Data Buffer Register- IDBRThe processor u

9-24 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit9.9.3 I2C Control Register- ICRThe processor uses th

Intel® PXA26x Processor Family Developer’s Manual 9-25Inter-Integrated Circuit Bus Interface Unit10 BEIEBUS ERROR INTERRUPT ENABLE:0 – Disable inter

9-26 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit9.9.4 I2C Status RegisterThe ISR signals I2C interru

Intel® PXA26x Processor Family Developer’s Manual 9-27Inter-Integrated Circuit Bus Interface UnitTable 9-12. I2C Status Register - ISR (Sheet 1 of

9-28 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit9.9.5 I2C Slave Address Register- ISARThe ISAR (see

Intel® PXA26x Processor Family Developer’s Manual 10-1Universal Asynchronous Receiver/Transmitter 10This chapter describes the three universal async

10-2 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter10.2 OverviewEach serial port contains a UART and a

Intel® PXA26x Processor Family Developer’s Manual 10-3Universal Asynchronous Receiver/Transmitter10.3 Signal DescriptionsTable 10-1 lists and descri

Intel® PXA26x Processor Family Developer’s Manual 2-7System ArchitectureNote: Clearing interrupts may take a delay. To allow the status bit to clear

10-4 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter10.4 UART Operational DescriptionFigure 10-1 shows t

Intel® PXA26x Processor Family Developer’s Manual 10-5Universal Asynchronous Receiver/TransmitterEach UART has two FIFOs: one transmit and one recei

10-6 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter.10.4.2.1 Receive Buffer Register (RBR)In non-FIFO m

Intel® PXA26x Processor Family Developer’s Manual 10-7Universal Asynchronous Receiver/Transmitter10.4.2.2 Transmit Holding Register (THR)In non-FIFO

10-8 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter10.4.2.4 Interrupt Enable Register (IER)The IER enab

Intel® PXA26x Processor Family Developer’s Manual 10-9Universal Asynchronous Receiver/TransmitterNote: When DMA requests are enabled and an interrup

10-10 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/TransmitterNote: To ensure that the DMA controller and program

Intel® PXA26x Processor Family Developer’s Manual 10-11Universal Asynchronous Receiver/TransmitterTable 10-8. Interrupt ConditionsPriority Level Int

10-12 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter10.4.2.6 FIFO Control Register (FCR)The FCR is a wr

Intel® PXA26x Processor Family Developer’s Manual 10-13Universal Asynchronous Receiver/TransmitterTable 10-11. FIFO Control Register – FCRBase+0x08

2-8 Intel® PXA26x Processor Family Developer’s Manual System ArchitectureByte and halfword accesses to internal registers are not permitted and yield

10-14 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter10.4.2.7 Line Control Register (LCR)The LCR specifi

Intel® PXA26x Processor Family Developer’s Manual 10-15Universal Asynchronous Receiver/Transmitter10.4.2.8 Line Status Register (LSR)The LSR provide

10-16 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/TransmitterTable 10-13. Line Status Register – LSR (Sheet 1 of

Intel® PXA26x Processor Family Developer’s Manual 10-17Universal Asynchronous Receiver/Transmitter10.4.2.9 Modem Control Register (MCR)The MCR uses

10-18 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/TransmitterTable 10-14. Modem Control Register – MCR (Sheet 1

Intel® PXA26x Processor Family Developer’s Manual 10-19Universal Asynchronous Receiver/Transmitter10.4.2.10 Modem Status Register (MSR)The MSR provi

10-20 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/TransmitterNote: When bit 0, 1, 2, or 3 is set, a modem status

Intel® PXA26x Processor Family Developer’s Manual 10-21Universal Asynchronous Receiver/Transmitter10.4.2.11 Scratchpad Register (SPR)The read/write

10-22 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/TransmitterAfter the processor reads one character from the re

Intel® PXA26x Processor Family Developer’s Manual 10-23Universal Asynchronous Receiver/TransmitterNote: Ensure that the DMAC has finished previous r

Intel® PXA26x Processor Family Developer’s Manual 2-9System Architecture• Sleep mode – low power mode that does not save state but keeps I/Os powere

10-24 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter10.4.6.2 OperationThe SIR modulation technique work

Intel® PXA26x Processor Family Developer’s Manual 10-25Universal Asynchronous Receiver/TransmitterThe top line in Figure 10-3 shows an asynchronous

10-26 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/TransmitterNote: The SIR TXD output pin is automatically held

Intel® PXA26x Processor Family Developer’s Manual 10-27Universal Asynchronous Receiver/Transmitter10.5.1 UART Register DifferencesThe default descri

10-28 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter

Intel® PXA26x Processor Family Developer’s Manual 11-1Fast Infrared Communication Port 11The Fast Infrared Communications Port (FICP) for the Intel®

11-2 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port11.2.1 Four-Position Pulse ModulationFour-position pulse modula

Intel® PXA26x Processor Family Developer’s Manual 11-3Fast Infrared Communication Port11.2.2 Frame FormatThe frame format used with 4-Mbps transmiss

11-4 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port11.2.3 Address FieldA transmitter uses the 8-bit address field

Intel® PXA26x Processor Family Developer’s Manual 11-5Fast Infrared Communication Port11.2.7 Baud Rate GenerationThe baud rate is derived by dividin

iv Intel® PXA26x Processor Family Developer’s Manual Contents3 Clocks and Power Manager ...

2-10 Intel® PXA26x Processor Family Developer’s Manual System ArchitecturenSDCS[0] OCZSDRAM CS FOR BANKS 0 THROUGH 3 (output):Connect to the chip sele

11-6 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication PortIf the data field contains any invalid chips (such as 0011, 101

Intel® PXA26x Processor Family Developer’s Manual 11-7Fast Infrared Communication PortAt the end of each transmitted frame, the FICP sends a pulse c

11-8 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication PortThe core must also read bytes from the FIFO until ICSR0[EIF] is

Intel® PXA26x Processor Family Developer’s Manual 11-9Fast Infrared Communication PortTable 11-2. Fast Infrared Communication Port Control Register

11-10 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port11.3.2 FICP Control Register 1FICP control register 1 (ICCR1)

Intel® PXA26x Processor Family Developer’s Manual 11-11Fast Infrared Communication Port11.3.3 FICP Control Register 2The FICP control register 2 (IC

11-12 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port11.3.4 FICP Data RegisterThe FICP data register (ICDR) is a 32

Intel® PXA26x Processor Family Developer’s Manual 11-13Fast Infrared Communication Porteach entry is removed, the EIF bit must be checked to determi

11-14 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port.11.3.6 FICP Status Register 1FICP status register 1 (ICSR1) c

Intel® PXA26x Processor Family Developer’s Manual 11-15Fast Infrared Communication Port.Table 11-7. Fast Infrared Communication Port Status Register

Intel® PXA26x Processor Family Developer’s Manual 2-11System ArchitecturenCS[5]/GPIO[33]ICOCZSTATIC CHIP SELECTS (output):Chip selects to static mem

11-16 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port11.4 Fast Infrared Communications Port Register LocationsTable

Intel® PXA26x Processor Family Developer’s Manual 12-1Universal Serial Bus Device Controller 12This section describes the Universal Serial Bus (USB)

12-2 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controllerservice request is generated when a packet has been recei

Intel® PXA26x Processor Family Developer’s Manual 12-3Universal Serial Bus Device ControllerData flow is relative to the USB host. IN packets repres

12-4 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controllerhost detects a disconnect when an SE0 persists for more t

Intel® PXA26x Processor Family Developer’s Manual 12-5Universal Serial Bus Device ControllerThe PID is 1 byte wide and always follows the sync field

12-6 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.3.4.2 Start of Frame Packet TypeAn SOF is a special ty

Intel® PXA26x Processor Family Developer’s Manual 12-7Universal Serial Bus Device Controller12.3.5 Transaction FormatsPackets are assembled into gro

12-8 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.3.5.3 Control Transaction TypeThe host uses control tr

Intel® PXA26x Processor Family Developer’s Manual 12-9Universal Serial Bus Device Controller• Data transfer direction: host to device, device to hos

2-12 Intel® PXA26x Processor Family Developer’s Manual System ArchitecturenPIOR/GPIO[50]ICOCZPCMCIA I/O READ (output):Performs read transactions from

12-10 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.3.7 ConfigurationIn response to the GET_DESCRIPTOR co

Intel® PXA26x Processor Family Developer’s Manual 12-11Universal Serial Bus Device Controller12.4.1.1 When GPIOn and GPIOx are Different PinsThe GPI

12-12 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.4.2 Bus-Powered DevicesThe processor does not support

Intel® PXA26x Processor Family Developer’s Manual 12-13Universal Serial Bus Device Controller14. When the host executes the STATUS OUT stage (zero-l

12-14 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller16. Software clears the UDC interrupt bit and returns fr

Intel® PXA26x Processor Family Developer’s Manual 12-15Universal Serial Bus Device Controllerthe wrong amount of data was sent, software cleans up a

12-16 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller1. During the SETUP VENDOR command, software enables the

Intel® PXA26x Processor Family Developer’s Manual 12-17Universal Serial Bus Device Controller2. The host PC sends a BULK-OUT.3. The DMA engine reads

12-18 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller1. During the SETUP VENDOR command, software enables the

Intel® PXA26x Processor Family Developer’s Manual 12-19Universal Serial Bus Device ControllerWhen software receives a SETUP VENDOR command to set up

Intel® PXA26x Processor Family Developer’s Manual 2-13System ArchitectureL_DD[12]/GPIO[70]ICOCZLCD DISPLAY DATA (output):Transfers pixel information

12-20 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller6. Return from interrupt.7. Steps 2 through 6 repeat unt

Intel® PXA26x Processor Family Developer’s Manual 12-21Universal Serial Bus Device Controllerb. If UDCCR[UDA] is a 1, there is currently no USB rese

12-22 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controlleraddress for the 16 x 8 data FIFO that can be used to tra

Intel® PXA26x Processor Family Developer’s Manual 12-23Universal Serial Bus Device Controller12.6.1.7 Reset Interrupt Request (RSTIR)The reset inter

12-24 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.2 UDC Endpoint 0 Control/Status Register (UDCCS0)Th

Intel® PXA26x Processor Family Developer’s Manual 12-25Universal Serial Bus Device Controller12.6.2.3 Flush Tx FIFO (FTF)The flush Tx FIFO bit trigg

12-26 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.3 UDC Endpoint x Control/Status Register (UDCCSx),

Intel® PXA26x Processor Family Developer’s Manual 12-27Universal Serial Bus Device Controller12.6.3.2 Transmit Packet Complete (TPC)The transmit pac

12-28 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.3.8 Transmit Short Packet (TSP)The software uses th

Intel® PXA26x Processor Family Developer’s Manual 12-29Universal Serial Bus Device Controller12.6.4.1 Receive FIFO Service (RFS)The receive FIFO ser

2-14 Intel® PXA26x Processor Family Developer’s Manual System ArchitectureFFRTS/GPIO[41]ICOCZ FULL FUNCTION UART REQUEST-TO-SEND (output):Pulled HighN

12-30 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.4.7 Receive FIFO Not Empty (RNE)The receive FIFO no

Intel® PXA26x Processor Family Developer’s Manual 12-31Universal Serial Bus Device Controller12.6.5 UDC Endpoint x Control/Status Register (UDCCSx),

12-32 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.5.3 Flush Tx FIFO (FTF)The Flush Tx FIFO bit trigge

Intel® PXA26x Processor Family Developer’s Manual 12-33Universal Serial Bus Device Controller12.6.6 UDC Endpoint x Control/Status Register (UDCCSx),

12-34 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.6.2 Receive Packet Complete (RPC)The receive packet

Intel® PXA26x Processor Family Developer’s Manual 12-35Universal Serial Bus Device Controller12.6.7 UDC Endpoint x Control/Status Register (UDCCSx),

12-36 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.7.2 Transmit Packet Complete (TPC)The transmit pack

Intel® PXA26x Processor Family Developer’s Manual 12-37Universal Serial Bus Device Controller12.6.7.8 Transmit Short Packet (TSP)Software uses the t

12-38 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.8.1 Interrupt Mask Endpoint x (IMx), Where x is 0 t

Intel® PXA26x Processor Family Developer’s Manual 12-39Universal Serial Bus Device Controller12.6.9.1 Interrupt Mask Endpoint x (IMx), where x is 8

Intel® PXA26x Processor Family Developer’s Manual 2-15System ArchitectureFFTXD/GPIO[39]ICOCZFULL FUNCTION UART TRANSMIT (output)MMC CHIP SELECT 1 (o

12-40 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.10 UDC Status/Interrupt Register 0 (USIR0)The UDC s

Intel® PXA26x Processor Family Developer’s Manual 12-41Universal Serial Bus Device Controller12.6.10.7 Endpoint 6 Interrupt Request (IR6)The interru

12-42 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.11.2 Endpoint 9 Interrupt Request (IR9)The interrup

Intel® PXA26x Processor Family Developer’s Manual 12-43Universal Serial Bus Device Controller12.6.12 UDC Frame Number High Register (UFNHR)The UDC f

12-44 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.12.3 Isochronous Packet Error Endpoint 9 (IPE9)The

Intel® PXA26x Processor Family Developer’s Manual 12-45Universal Serial Bus Device Controller12.6.13 UDC Frame Number Low Register (UFNLR)The UDC fr

12-46 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.15 UDC Endpoint 0 Data Register (UDDR0)The UDC endp

Intel® PXA26x Processor Family Developer’s Manual 12-47Universal Serial Bus Device Controller12.6.16 UDC Data Register x (UDDRx), Where x is 1, 6, o

12-48 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or

Intel® PXA26x Processor Family Developer’s Manual 12-49Universal Serial Bus Device Controller12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, o

2-16 Intel® PXA26x Processor Family Developer’s Manual System ArchitectureAC97 Controller and I2S Controller PinsBITCLK/GPIO[28]ICOCZAC97 AUDIO PORT B

12-50 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller12.6.21 UDC Register LocationsTable 12-32 shows the regi

Intel® PXA26x Processor Family Developer’s Manual 12-51Universal Serial Bus Device Controller0h 4060 0180 UDDR2 UDC Endpoint 2 Data Register0h 4060

12-52 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller

Intel® PXA26x Processor Family Developer’s Manual 13-1AC97 Controller Unit 1313.1 OverviewThe AC97 Controller Unit (ACUNIT) of the Intel® PXA26x Pro

13-2 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.3 Signal DescriptionThe AC97 signals form the AC-link, which is a point-

Intel® PXA26x Processor Family Developer’s Manual 13-3AC97 Controller Unit13.4 AC-link Digital Serial Interface ProtocolEach AC97 codec incorporates

13-4 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller UnitThe ACUNIT provides synchronization for all data transaction on the AC-link

Intel® PXA26x Processor Family Developer’s Manual 13-5AC97 Controller UnitA new audio output frame begins with a low-to-high SYNC transition synchro

13-6 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller UnitNote: When the ACUNIT transmits mono audio sample streams, software must en

Intel® PXA26x Processor Family Developer’s Manual 13-7AC97 Controller Unit3. Write a non-zero value (0b01, 0b10, 0b11) to the codec ID field (slot 0

Intel® PXA26x Processor Family Developer’s Manual 2-17System ArchitectureGPIO[14:2] ICOCZGENERAL PURPOSE I/O:More wake-up sources for sleep mode.Pul

13-8 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.4.1.6 Slot 5: Modem Line CodecAudio output frame slot 5 contains the MSB

Intel® PXA26x Processor Family Developer’s Manual 13-9AC97 Controller UnitA new audio input frame begins when SYNC transitions from low to high. The

13-10 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.4.2.2 Slot 1: Status Address Port/SLOTREQ bitsThe status port monitors

Intel® PXA26x Processor Family Developer’s Manual 13-11AC97 Controller UnitNote: Slot requests for slots 3 and 4 are always set or cleared in tandem

13-12 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.4.2.9 Slot 12: I/O StatusThe GPIOs configured as inputs return their st

Intel® PXA26x Processor Family Developer’s Manual 13-13AC97 Controller Unit13.5.2 Waking up the AC-link13.5.2.1 Wake up triggered by the CodecTo wak

13-14 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.5.2.2.1 Cold AC97 ResetA cold reset is generated when the nACRESET pin

Intel® PXA26x Processor Family Developer’s Manual 13-15AC97 Controller UnitNote: After it is enabled, the ACUNIT requests the DMA immediately to fil

13-16 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unitdoes not set the codec-ready bit, GCR[PCRDY] for the primary codec or GCR[

Intel® PXA26x Processor Family Developer’s Manual 13-17AC97 Controller Unittransmit valid data in certain frames. For example, if the controller sen

2-18 Intel® PXA26x Processor Family Developer’s Manual System ArchitectureMiscellaneous PinsBOOT_SEL[2:0]ICBOOT SELECT PINS (input):Indicates type of

13-18 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.1.2 Receive FIFO ErrorsChannel-specific status bits are updated durin

Intel® PXA26x Processor Family Developer’s Manual 13-19AC97 Controller Unit• Audio codec registers• Modem codec registersChannel specific data regis

13-20 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.3.2 Global Control Register0x4050_0118 MISR Modem In Status Register0

Intel® PXA26x Processor Family Developer’s Manual 13-21AC97 Controller Unit7:6 — Reserved5 SECRES_IENSECONDARY RESUME INTERRUPT ENABLE:0 – Interrupt

13-22 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.3.3 Global Status Register (GSR)Table 13-9. Global Status Register (S

Intel® PXA26x Processor Family Developer’s Manual 13-23AC97 Controller Unit7MINTMIC IN INTERRUPT (MINT):0 – None of the Mic-in channel interrupts oc

13-24 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.3.4 PCM-Out Control Register (POCR)13.8.3.5 PCM-In Control Register (

Intel® PXA26x Processor Family Developer’s Manual 13-25AC97 Controller Unit13.8.3.6 PCM-Out Status Register (POSR)13.8.3.7 PCM_In Status Register (P

13-26 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.3.8 Codec Access Register (CAR)13.8.3.9 PCM Data Register (PCDR)Writi

Intel® PXA26x Processor Family Developer’s Manual 13-27AC97 Controller Unit13.8.3.10 Mic-In Control Register (MCCR)Figure 13-9. PCM Transmit and Rec

Intel® PXA26x Processor Family Developer’s Manual 2-19System ArchitectureTMS ICJTAG TEST MODE SELECT (input):Selects the test mode required from the

13-28 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.3.11 Mic-In Status Register (MCSR)13.8.3.12 Mic-In Data Register (MCD

Intel® PXA26x Processor Family Developer’s Manual 13-29AC97 Controller Unit13.8.3.13 Modem-Out Control Register (MOCR)Figure 13-10. Mic-in Receive-O

13-30 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.3.14 Modem-In Control Register (MICR)13.8.3.15 Modem-Out Status Regis

Intel® PXA26x Processor Family Developer’s Manual 13-31AC97 Controller Unit13.8.3.16 Modem-In Status Register (MISR)13.8.3.17 Modem Data Register (M

13-32 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit13.8.3.18 Accessing Codec Registers Each codec has up to sixty-four 16-bit

Intel® PXA26x Processor Family Developer’s Manual 13-33AC97 Controller UnitTable 13-24. Address Mapping for Codec Registers (Sheet 1 of 2)7-bit Code

13-34 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit0x46 0x4050_028C 0x4050_038C 0x4050_048C 0x4050_058C0x48 0x4050_0290 0x405

Intel® PXA26x Processor Family Developer’s Manual 14-1Inter-Integrated Circuit Sound Controller 14Inter-Integrated Circuit Sound (I2S) is a protocol

14-2 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller14.2 Signal DescriptionsSYSCLK is the clock on which a

Intel® PXA26x Processor Family Developer’s Manual 14-3Inter-Integrated Circuit Sound ControllerTo configure SYNC and SDATA_OUT as outputs, follow th

Intel® PXA26x Processor Family Developer’s Manual v Contents4.1.2 GPIO Alternate Functions...

2-20 Intel® PXA26x Processor Family Developer’s Manual System ArchitectureASSPSFRM/GPIO[31]ICOCZAUDIO SYNCHRONOUS SERIAL PORT FRAME SIGNALPulled HighN

14-4 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller3. Optional: Programmed I/O may be used for priming th

Intel® PXA26x Processor Family Developer’s Manual 14-5Inter-Integrated Circuit Sound ControllerAsserting the DREC bit in SACR1 has the following eff

14-6 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound ControllerThe BITCLK, as shown in Table 14-2, is different for d

Intel® PXA26x Processor Family Developer’s Manual 14-7Inter-Integrated Circuit Sound ControllerFigure 14-1 and Figure 14-2 provide timing diagrams t

14-8 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller• The Status Register signals the state of the FIFO bu

Intel® PXA26x Processor Family Developer’s Manual 14-9Inter-Integrated Circuit Sound ControllerNOTES:† If ENB is toggled in the middle of a normal o

14-10 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller14.6.1.2 Suggested TFTH and RFTH for DMA servicingThe

Intel® PXA26x Processor Family Developer’s Manual 14-11Inter-Integrated Circuit Sound Controller† SACR1 bits DRPL, DREC, and AMSL cross clock domain

14-12 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound ControllerTable 14-7. SASR0 Bit DescriptionsPhysical Address0x4

Intel® PXA26x Processor Family Developer’s Manual 14-13Inter-Integrated Circuit Sound Controller14.6.4 Serial Audio Clock Divider Register (SADIV)Th

Intel® PXA26x Processor Family Developer’s Manual 2-21System Architecture2.13 Register Address SummaryTable 2-8 lists the registers present in the P

14-14 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller14.6.6 Serial Audio Interrupt Mask Register (SAIMR)Wr

Intel® PXA26x Processor Family Developer’s Manual 14-15Inter-Integrated Circuit Sound ControllerFigure 14-3. Transmit and Receive FIFO Accesses Thro

14-16 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller14.7 InterruptsThe following SASR0 status bits, if en

Intel® PXA26x Processor Family Developer’s Manual 15-1MultiMediaCard Controller 1515.1 OverviewThe Intel® PXA26x Processor Family MultiMediaCard (MM

15-2 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard ControllerThe MMC bus connects the card stack to the controller. The software an

Intel® PXA26x Processor Family Developer’s Manual 15-3MultiMediaCard Controller. In SPI mode, not all commands are available. The available commands

15-4 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard ControllerNote: One- and three-byte data transfers are not supported with this c

Intel® PXA26x Processor Family Developer’s Manual 15-5MultiMediaCard ControllerThe MMCLK, MMCCS0, and MMCCS1 signals are routed through alternate fu

15-6 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controlleraddress in the argument portion of the command token that is protected

Intel® PXA26x Processor Family Developer’s Manual 15-7MultiMediaCard ControllerThe command token is protected with a 7-bit CRC. The card always send

2-22 Intel® PXA26x Processor Family Developer’s Manual System Architecture0x4000 001C DCSR7 DMA Control / Status Register for Channel 70x4000 0020 DCS

15-8 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller3. Restart the clock.Software must not stop the clock when it attempts

Intel® PXA26x Processor Family Developer’s Manual 15-9MultiMediaCard Controller15.2.8.2 Receive Data FIFO, MMC_RXFIFOThe two receive data FIFOs are

15-10 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller15.2.8.3 Transmit Data FIFO, MMC_TXFIFOThe two transmit data FIFOs ar

Intel® PXA26x Processor Family Developer’s Manual 15-11MultiMediaCard ControllerFor the DMA, use three descriptors of 32 bytes and 32-byte bursts an

15-12 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller—MMC_CLKRT—MMC_SPI— MMC_RESTO4. Start the clock5. Write 0x7b to the M

Intel® PXA26x Processor Family Developer’s Manual 15-13MultiMediaCard ControllerThe MMC controller performs data transactions in all the basic modes

15-14 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard ControllerIn a block data read, the following parameters must be specified:• Th

Intel® PXA26x Processor Family Developer’s Manual 15-15MultiMediaCard Controller• The data transfer is a read.• The data transfer is in stream mode.

15-16 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller15.4.1 Start and Stop ClockThe set of registers is accessed by stoppi

Intel® PXA26x Processor Family Developer’s Manual 15-17MultiMediaCard ControllerThe software must not make changes in the set of registers until the

Intel® PXA26x Processor Family Developer’s Manual 2-23System Architecture0x4000 0178 DRCMR30 Request to Channel Map Register for USB endpoint 6 Requ

15-18 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller5. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates t

Intel® PXA26x Processor Family Developer’s Manual 15-19MultiMediaCard ControllerThe multiple block write mode also requires a stop transmission comm

15-20 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller8. Set MMC_I_MASK to 0x1d.9. Wait for MMC_I_REG[PRG_DONE] interrupt.

Intel® PXA26x Processor Family Developer’s Manual 15-21MultiMediaCard Controller15.5 MultiMediaCard Controller Register DescriptionsThe MMC controll

15-22 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller15.5.2 MMC_STAT RegisterThe MMC_STAT Register is the status register

Intel® PXA26x Processor Family Developer’s Manual 15-23MultiMediaCard Controller15.5.3 MMC_CLKRT RegisterThe MMC_CLKRT register specifies the freque

15-24 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard ControllerThe software can only write this register after the clock is turned o

Intel® PXA26x Processor Family Developer’s Manual 15-25MultiMediaCard Controller15.5.5 MMC_CMDAT RegisterThe MMC_CMDAT register controls the command

15-26 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller15.5.6 MMC_RESTO RegisterThe MMC_RESTO register controls the number o

Intel® PXA26x Processor Family Developer’s Manual 15-27MultiMediaCard Controller15.5.7 MMC_RDTO RegisterThe MMC_RDTO register determines the length

2-24 Intel® PXA26x Processor Family Developer’s Manual System Architecture0x4000 0278 DTADR7 DMA Target Address Register Channel 70x4000 027C DCMD7 DM

15-28 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller15.5.8 MMC_BLKLEN RegisterThe MMC_BLKLEN register specifies the numbe

Intel® PXA26x Processor Family Developer’s Manual 15-29MultiMediaCard Controller15.5.11 MMC_I_MASK RegisterThe MMC_I_MASK register masks off the var

15-30 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller15.5.12 MMC_I_REG RegisterThe MMC_I_REG register shows the currently

Intel® PXA26x Processor Family Developer’s Manual 15-31MultiMediaCard Controller15.5.13 MMC_CMD RegisterThe MMC_CMD register specifies the command n

15-32 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard ControllerTable 15-18. MMC_CMD RegisterPhysical Address4110_0030MMC_CMD Registe

Intel® PXA26x Processor Family Developer’s Manual 15-33MultiMediaCard Controller010110 CMD22 Reserved010111 CMD23 Reserved011000 CMD24 MMC/SPI WRITE

15-34 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller15.5.14 MMC_ARGH RegisterThe MMC_ARGH register specifies the upper 16

Intel® PXA26x Processor Family Developer’s Manual 15-35MultiMediaCard Controller15.5.16 MMC_RES FIFO (read only)The MMC_RES FIFO contains the respon

15-36 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard ControllerTable 15-24. MMC_TXFIFO, FIFO EntryPhysical Address4110_0044MMC_TXFIF

Intel® PXA26x Processor Family Developer’s Manual 16-1Network/Audio Synchronous Serial Protocol Serial Ports 16This chapter describes the signal def

Intel® PXA26x Processor Family Developer’s Manual 2-25System Architecture0x4010 000C FFLCR Line Control Register (read/write)0x4010 0010 FFMCR Modem

16-2 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports16.3 Signal DescriptionTable 16-1 lists t

Intel® PXA26x Processor Family Developer’s Manual 16-3Network/Audio Synchronous Serial Protocol Serial Ports16.4.1 Processor and DMA FIFO AccessThe

16-4 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports16.4.2.2 Removing Trailing BytesIn this c

Intel® PXA26x Processor Family Developer’s Manual 16-5Network/Audio Synchronous Serial Protocol Serial Ports• For PSP, the protocol allows for the c

16-6 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports16.4.3.2 SPI Protocol DetailsThe SPI prot

Intel® PXA26x Processor Family Developer’s Manual 16-7Network/Audio Synchronous Serial Protocol Serial PortsFor back-to-back transfers, frames start

16-8 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial PortsThe state of SSPRXD is undefined before t

Intel® PXA26x Processor Family Developer’s Manual 16-9Network/Audio Synchronous Serial Protocol Serial PortsNote: When configured as either master o

16-10 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial PortsNote: When configured master the SSP por

Intel® PXA26x Processor Family Developer’s Manual 16-11Network/Audio Synchronous Serial Protocol Serial Portsclocks programmed in the field SSPSP[SF

2-26 Intel® PXA26x Processor Family Developer’s Manual System Architecture0x4040 0064through0x4040 007C— reserved0x4040 0080 SADR Serial Audio Data Re

16-12 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial PortsNote: The SSPSFRM delay must not extend

Intel® PXA26x Processor Family Developer’s Manual 16-13Network/Audio Synchronous Serial Protocol Serial Ports(SSCR1[SFRMDIR] is set) if the assertio

16-14 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial PortsNote: If SSPSCLK is an input, the device

Intel® PXA26x Processor Family Developer’s Manual 16-15Network/Audio Synchronous Serial Protocol Serial PortsNote: SSCR1[TTELP] must be 0 for Nation

16-16 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial PortsSSCR1[TTELP] can only be set to 1 in PSP

Intel® PXA26x Processor Family Developer’s Manual 16-17Network/Audio Synchronous Serial Protocol Serial Ports16.4.5 FIFO OperationTwo separate and i

16-18 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports16.5 SSP Port Register DescriptionsEach

Intel® PXA26x Processor Family Developer’s Manual 16-19Network/Audio Synchronous Serial Protocol Serial PortsTable 16-3. SSCR0 Bit Definitions (Shee

16-20 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports5:4 R/W FRFFRAME FORMAT:SELECTS which fr

Intel® PXA26x Processor Family Developer’s Manual 16-21Network/Audio Synchronous Serial Protocol Serial Ports16.5.2 SSP Control Register 1 (SSCR1)SS

Intel® PXA26x Processor Family Developer’s Manual 2-27System Architecture0x4050 0300through0x4050 03FC— Secondary Audio codec Registers0x4050 0400th

16-22 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports29 R/W EBCEIBIT COUNT ERROR INTERRUPT MA

Intel® PXA26x Processor Family Developer’s Manual 16-23Network/Audio Synchronous Serial Protocol Serial Ports24 R/W SFRMDIRSSP FRAME DIRECTION:Deter

16-24 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports21 R/W TSRETRANSMIT SERVICE REQUEST ENAB

Intel® PXA26x Processor Family Developer’s Manual 16-25Network/Audio Synchronous Serial Protocol Serial Ports14 R/W EFWRENABLE FIFO WRITE/READ (test

16-26 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports3R/WSPOMOTOROLA SPI SSPSCLK POLARITY SET

Intel® PXA26x Processor Family Developer’s Manual 16-27Network/Audio Synchronous Serial Protocol Serial Ports16.5.3 SSP Programmable Serial Protocol

16-28 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports16.5.4 SSP Time Out Register (SSTO)SSP T

Intel® PXA26x Processor Family Developer’s Manual 16-29Network/Audio Synchronous Serial Protocol Serial Ports16.5.5 SSP Interrupt Test Register (SSI

16-30 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports16.5.6 SSP Status Register (SSSR)SSSR, s

Intel® PXA26x Processor Family Developer’s Manual 16-31Network/Audio Synchronous Serial Protocol Serial PortsTable 16-8. SSSR Bit Definitions (Sheet

2-28 Intel® PXA26x Processor Family Developer’s Manual System Architecture0x4060 0600 UDDR6 UDC Endpoint 6 Data Register0x4060 0680 UDDR7 UDC Endpoint

16-32 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports15:12 R RFLRECEIVE FIFO LEVEL:The number

Intel® PXA26x Processor Family Developer’s Manual 16-33Network/Audio Synchronous Serial Protocol Serial Ports5 R TFSTRANSMIT FIFO SERVICE REQUEST:In

16-34 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports16.5.7 SSP Data Register (SSDR)SSDR, sho

Intel® PXA26x Processor Family Developer’s Manual 16-35Network/Audio Synchronous Serial Protocol Serial PortsTable 16-10. NSSP Register Address MapP

16-36 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports

Intel® PXA26x Processor Family Developer’s Manual 17-1Hardware UART 17This chapter describes the signal definitions and operation of the Intel® PXA2

17-2 Intel® PXA26x Processor Family Developer’s Manual Hardware UART17.2 FeaturesThe HWUART has the following features:• Functionally compatible with

Intel® PXA26x Processor Family Developer’s Manual 17-3Hardware UART• Slow infrared asynchronous interface that conforms to the Infrared Data Associa

17-4 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTReceive data sample counter frequency is 16 times the value of the bit frequency.

Intel® PXA26x Processor Family Developer’s Manual 17-5Hardware UART17.4.1 ResetThe UART is disabled on reset. To enable the UART, software must prog

Intel® PXA26x Processor Family Developer’s Manual 2-29System Architecture0x4090 000C RTTR RTC Timer Trim RegisterOS Timer 0x40A0 00000x40A0 0000 OSM

17-6 Intel® PXA26x Processor Family Developer’s Manual Hardware UART17.4.2.1.3 Transmit InterruptTransmit interrupts can only occur when the transmit

Intel® PXA26x Processor Family Developer’s Manual 17-7Hardware UARTNote: When DMA requests are enabled and an interrupt occurs, software must first

17-8 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTWhen in Full or Half-Autoflow mode, nCTS is asserted by the remote receiver when t

Intel® PXA26x Processor Family Developer’s Manual 17-9Hardware UARTThe SIR interface does not contain the actual IR LED driver or the receiver ampli

17-10 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTFigure 17-4. XMODE Example.Note: The SIR TXD output pin is automatically held dea

Intel® PXA26x Processor Family Developer’s Manual 17-11Hardware UART 17.5.2 Transmit Holding Register (THR)In non-FIFO mode, the Transmit Holding Re

17-12 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTLoad these divisor latches during initialization to ensure that the baud rate gen

Intel® PXA26x Processor Family Developer’s Manual 17-13Hardware UART17.5.4 Interrupt Enable Register (IER)The IER enables the five types of interrup

17-14 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTNote: To ensure that the DMA controller and programmed I/O do not access the same

Intel® PXA26x Processor Family Developer’s Manual 17-15Hardware UARTTable 17-7. Interrupt ConditionsPriority Level Interrupt origin1 (highest) Recei

vi Intel® PXA26x Processor Family Developer’s Manual Contents6.2 Functional Description ...

2-30 Intel® PXA26x Processor Family Developer’s Manual System Architecture0x40E0 0038 GRER2 GPIO Rising-Edge Detect Register GPIO<80:64>0x40E0 0

17-16 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTTable 17-9 shows the priority, type, and source of the Interrupt Identification R

Intel® PXA26x Processor Family Developer’s Manual 17-17Hardware UART17.5.6 FIFO Control Register (FCR)The FIFO Control Register (FCR) is a write-onl

17-18 Intel® PXA26x Processor Family Developer’s Manual Hardware UART17.5.7 Receive FIFO Occupancy Register (FOR)The Receive FIFO Occupancy Register s

Intel® PXA26x Processor Family Developer’s Manual 17-19Hardware UARTAll reserved bits are read as unknown and must be written with a 0. The register

17-20 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTNote: Auto-baud rate detection is not supported with slow infrared Mode.See Secti

Intel® PXA26x Processor Family Developer’s Manual 17-21Hardware UART17.5.10 Line Control Register (LCR)The Line Control Register (LCR) specifies the

17-22 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTTable 17-14. LCR Bit Definitions (Sheet 1 of 2)Physical Address0x4160_000CLine Co

Intel® PXA26x Processor Family Developer’s Manual 17-23Hardware UART17.5.11 Line Status Register (LSR)The LSR provides data transfer status informat

17-24 Intel® PXA26x Processor Family Developer’s Manual Hardware UARTSee Section 17.4.2.3, “FIFO DMA Mode Operation” for details on using the DMA to r

Intel® PXA26x Processor Family Developer’s Manual 17-25Hardware UART5RTDRQTRANSMIT DATA REQUEST:Indicates that the UART is ready to accept a new cha

Intel® PXA26x Processor Family Developer’s Manual 2-31System Architecture0x4110 0004 MMC_STAT MMC Status Register (read only)0x4110 0008 MMC_CLKRT M

17-26 Intel® PXA26x Processor Family Developer’s Manual Hardware UART17.5.12 Modem Control Register (MCR)The Modem Control Register (MCR) uses the mod

Intel® PXA26x Processor Family Developer’s Manual 17-27Hardware UARTTable 17-16. MCR Bit Definitions (Sheet 1 of 2)Physical Address0x4160_0010Modem

17-28 Intel® PXA26x Processor Family Developer’s Manual Hardware UART17.5.13 Modem Status Register (MSR)The Modem Status Register (MSR) provides the c

Intel® PXA26x Processor Family Developer’s Manual 17-29Hardware UARTNote: When bit 0, 1, 2, or 3 is set, a Modem Status interrupt is generated if IE

17-30 Intel® PXA26x Processor Family Developer’s Manual Hardware UART17.5.15 Infrared Selection Register (ISR)Each UART can manage an IrDA module asso

Intel® PXA26x Processor Family Developer’s Manual 17-31Hardware UART17.6 Hardware UART Register SummaryTable 17-20 contains the register addresses f

17-32 Intel® PXA26x Processor Family Developer’s Manual Hardware UART0x4160 0008 X HWIIR “Interrupt Identification Register (IIR)” (read only)0x4160 0

Intel® PXA26x Processor Family Developer’s Manual 18-1Internal Flash 18This chapter describes the flash interface for the Intel® PXA26x Processor Fa

18-2 Intel® PXA26x Processor Family Developer’s Manual Internal FlashIf watchdog reset is not necessary, a secondary GPIO can control nRESET_OUT using

Intel® PXA26x Processor Family Developer’s Manual 18-3Internal FlashWarning: Using a memory-clock frequency above 133 MHz is not allowed in synchron

2-32 Intel® PXA26x Processor Family Developer’s Manual System Architecture0x4160 0000 HWTHR Transmit Holding register (write only)0x4160 0004 HWIER In

18-4 Intel® PXA26x Processor Family Developer’s Manual Internal Flash;//--- Configure the processor in synchronous mode;//--- Can be used with normal

Intel® PXA26x Processor Family Developer’s Manual 18-5Internal Flash;//--- Fill up registers with correct values -- 50 MHzSDCLK0_50MHz;//--- Check f

18-6 Intel® PXA26x Processor Family Developer’s Manual Internal Flashstrh r9, [r8] ;/* No need for cache alignment since second flash chip */ldrh r9,

Intel® PXA26x Processor Family Developer’s Manual 18-7Internal Flash

Intel® PXA26x Processor Family Developer’s Manual 2-33System Architecture2.14 Memory MapFigure 2-3 on page 2-35 and Figure 2-2 on page 2-34 show the

2-34 Intel® PXA26x Processor Family Developer’s Manual System ArchitectureFigure 2-2. Memory Map (Part One) — From 0x8000 0000 to 0xFFFF FFFF Reserved

Intel® PXA26x Processor Family Developer’s Manual 2-35System ArchitectureFigure 2-3. Memory Map (Part Two) — From 0x0000 0000 to 0x7FFF FFFF Reserve

2-36 Intel® PXA26x Processor Family Developer’s Manual System Architecture

Intel® PXA26x Processor Family Developer’s Manual 3-1Clocks and Power Manager 3The clocks and power manager for the Intel® PXA26x Processor Family con

3-2 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.2 Power Manager IntroductionThe clocks and power manager can place th

Intel® PXA26x Processor Family Developer’s Manual 3-3 Clocks and Power ManagerFigure 3-1 shows a functional representation of the clocking network. “L

Intel® PXA26x Processor Family Developer’s Manual vii Contents7.2.3 Resetting the Controller...

3-4 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.3.1 32.768-KHz OscillatorThe 32.768-KHz oscillator is a low-power, lo

Intel® PXA26x Processor Family Developer’s Manual 3-5 Clocks and Power Manager3.3.4 95.85-MHz Peripheral Phase Locked LoopThe 95.85-MHz PLL is the clo

3-6 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.3.5 147.46-MHz Peripheral Phase Locked LoopThe 147.46-MHz PLL is the

Intel® PXA26x Processor Family Developer’s Manual 3-7 Clocks and Power Manager3.4.1 Hardware ResetTo invoke a hardware reset and reset all units in th

3-8 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.4.2.2 Behavior During Watchdog ResetDuring watchdog reset, all units

Intel® PXA26x Processor Family Developer’s Manual 3-9 Clocks and Power ManagerGPIO reset does not function in sleep mode because all GPIO pins’ altern

3-10 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.4.5.1 Entering Turbo ModeThe ratio between the run mode processor cl

Intel® PXA26x Processor Family Developer’s Manual 3-11 Clocks and Power ManagerDuring idle mode these resources are active: • System unit modules (rea

3-12 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power ManagerSoftware must then shut down the system and enter sleep mode. See Sect

Intel® PXA26x Processor Family Developer’s Manual 3-13 Clocks and Power Manager3. Perform a frequency change sequence to 33MHz mode. The CCCR value fo

viii Intel® PXA26x Processor Family Developer’s Manual Contents9.3.2 Inter-Integrated Circuit Bus Interface Modes...

3-14 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager2. Disable the LCD controller or configure it to avoid the effects of

Intel® PXA26x Processor Family Developer’s Manual 3-15 Clocks and Power ManagerIf hardware or watchdog reset is asserted during the frequency change s

3-16 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager• A power enable input pin that enables the primary supply output conn

Intel® PXA26x Processor Family Developer’s Manual 3-17 Clocks and Power Manager— PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2)— PM Wake-up E

3-18 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Managerin software by reading the Saved Program Status Register (SPSR) to see

Intel® PXA26x Processor Family Developer’s Manual 3-19 Clocks and Power ManagerRefer to Table 2-6, “Pin & Signal Descriptions for the PXA26x Proce

3-20 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager— The power manager wake-up source registers (PWER, PRER, and PFER) ar

Intel® PXA26x Processor Family Developer’s Manual 3-21 Clocks and Power Manager.Table 3-5. Power Mode Exit Sequence Table StepDescription of ActionTu

3-22 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.5 Power Manager RegistersThis section describes the 32-bit registers

Intel® PXA26x Processor Family Developer’s Manual 3-23 Clocks and Power Manager3.5.1 Power Manager Control Register (PMCR)Use the PMCR, refer to Table

Intel® PXA26x Processor Family Developer’s Manual ix Contents11.2.1 Four-Position Pulse Modulation...

3-24 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.5.2 Power Manager General Configuration Register (PCFR)Use the PCFR,

Intel® PXA26x Processor Family Developer’s Manual 3-25 Clocks and Power Manager3.5.3 Power Manager Wake-Up Enable Register (PWER)PWER, refer to Table

3-26 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)The PRER,

Intel® PXA26x Processor Family Developer’s Manual 3-27 Clocks and Power Manager3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)The PFER,

3-28 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)The PEDR, r

Intel® PXA26x Processor Family Developer’s Manual 3-29 Clocks and Power Manager3.5.7 Power Manager Sleep Status Register (PSSR)The PSSR, refer to Tabl

3-30 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager3.5.8 Power Manager Scratch Pad Register (PSPR)The power manager conta

Intel® PXA26x Processor Family Developer’s Manual 3-31 Clocks and Power Manager3.5.9 Power Manager Fast Sleep Wake Up Configuration Register (PMFWR)Th

3-32 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power ManagerWarning: Because GPIO[89:86] were previously dedicated pins, they only

Intel® PXA26x Processor Family Developer’s Manual 3-33 Clocks and Power Manager3.5.11 Reset Controller Status Register (RCSR)The CPU uses the RCSR, re