Intel PXA26X User Manual download pdf (Page 174)

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5-16 Intel® PXA26x Processor Family Developer’s Manual

Direct Memory Access Controller

3. At the end of the transfer, DTADRx is increased by the smaller value of DCMDx[LENGTH]

and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same number.

Note: The process shown for a flow-through DMA write to an external peripheral indicates that the

external address increases. Some external peripherals, such as FIFOs, do not require an increment

in the external address.

For a flow-through DMA write to an external peripheral, use these settings for the DMAC register

bits:

• DSADR[SRCADDR] = companion chip address

• DTADR[TRGADDR] = external memory address.

• DCMD[INCSRCADDR] = 0

• DCMD[INCTRGADDR] = 1

• DCMD[FLOWSRC] = 1

• DCMD[FLOWTRG] = 0

5.2.4 Memory-to-Memory Moves

Memory-to-memory moves do not involve the DREQ and PREQ request signals. The processor

writes to the DCSR[RUN] bit and a channel is configured for a memory-to-memory move. The

DCMDx[FLOWSRC] and the DCMD[FLOWTRG] bits must be set to 0.

If DCMD[IRQEN] is set to a 1, a DMA interrupt is requested at the end of the last cycle associated

with the byte that caused DCMDx[LENGTH] to decrease from 1 to 0.

A flow-through DMA memory-to-memory read or write goes through the following steps:

1. The processor writes to the DCSR[RUN] register bit and starts the memory-to-memory

moves.

2. If the processor is in the Descriptor Fetch Mode, the channel configured for the move fetches

the four-word descriptor. The channel transfers data without waiting for PREQ or DREQ to be

asserted. The smaller value of DCMDx[SIZE] or DCMDx[LENGTH] specifies the number of

bytes to be transferred.

3. The DMAC sends a request to the memory controller to read the number of bytes addressed by

DSADRx[31:0] into a 32-byte staging buffer in the DMAC.

4. The DMAC generates a write cycle to the location addressed in DTADRx[31:0].

5. At the end of the transfer, DSADRx and DTADRx are increased by the smaller value of

DCMD[SIZE] and DCMDx[LENGTH]. If DCMD[SIZE] is smaller than DCMDx[LENGTH],

DCMDx[LENGTH] is decreased by DCMD[SIZE]. If DCMD[SIZE] is equal to or larger than

DCMDx[LENGTH], DCMDx[LENGTH] is zero.

Note: The process shown for a memory-to-memory transfer indicates that the external address increases.

Some external peripherals, such as FIFOs, do not require an increment in the external address.

For a memory-to-memory read or write, use these settings for the DMAC registers:

• DSADR[SRCADDR] = external memory address

• DTADR[TRGADDR] = external memory address

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