Intel PXA26X User Manual download pdf (Page 6)

vi Intel® PXA26x Processor Family Developer’s Manual

Contents

6.2 Functional Description .......................................................................................................6-2

6.2.1 SDRAM Interface Overview..................................................................................6-2

6.2.2 Static Memory Interface / Variable Latency I/O Interface .....................................6-3

6.2.3 16-Bit PC Card / Compact Flash Interface ...........................................................6-4

6.3 Memory System Examples................................................................................................6-4

6.4 Memory Accesses .............................................................................................................6-6

6.4.1 Reads and Writes .................................................................................................6-7

6.4.2 Aborts and Nonexistent Memory ..........................................................................6-7

6.5 Memory Configuration Registers .......................................................................................6-8

6.6 Synchronous DRAM Memory Interface.............................................................................6-9

6.6.1 SDRAM MDCNFG Register..................................................................................6-9

6.6.2 SDRAM Mode Register Set Configuration Register ...........................................6-12

6.6.3 SDRAM MDREFR Register................................................................................6-14

6.6.4 SDRAM Memory Options ...................................................................................6-17

6.6.5 SDRAM Command Overview .............................................................................6-25

6.6.6 SDRAM Waveforms............................................................................................6-27

6.7 Synchronous Static Memory Interface.............................................................................6-30

6.7.1 Synchronous Static Memory Configuration Register..........................................6-30

6.7.2 Synchronous Static Memory Mode Register Set Configuration Register ...........6-36

6.7.3 Synchronous Static Memory Timing Diagrams...................................................6-37

6.7.4 Non-SDRAM Timing SXMEM Operation ............................................................6-38

6.8 Asynchronous Static Memory..........................................................................................6-41

6.8.1 Static Memory Interface......................................................................................6-41

6.8.2 Asynchronous Static Memory Control Registers (MSC0 – 2).............................6-44

6.8.3 ROM Interface ....................................................................................................6-48

6.8.4 SRAM Interface Overview ..................................................................................6-51

6.8.5 Variable Latency I/O (VLIO) Interface Overview.................................................6-53

6.8.6 FLASH Memory Interface ...................................................................................6-56

6.9 16-Bit PC Card/Compact Flash Interface ........................................................................6-57

6.9.1 Expansion Memory Timing Configuration Register ............................................6-58

6.9.2 Expansion Memory Configuration Register (MECR) ..........................................6-61

6.9.3 16-Bit PC Card Overview....................................................................................6-61

6.9.4 External Logic for 16-Bit PC Card Implementation.............................................6-64

6.9.5 Expansion Card Interface Timing Diagrams and Parameters ............................6-67

6.10 Companion Chip Interface...............................................................................................6-68

6.10.1 Alternate Bus Master Mode ................................................................................6-70

6.11 Options and Settings for Boot Memory............................................................................6-72

6.11.1 Alternate Booting ................................................................................................6-72

6.11.2 Boot Time Defaults .............................................................................................6-72

6.11.3 Memory Interface Reset and Initialization...........................................................6-75

6.12 Hardware, Watchdog, or Sleep Reset Operation ............................................................6-76

6.13 General Purpose Input/Output Reset Procedure.............................................................6-78

7 Liquid Crystal Display Controller ..................................................................................................7-1

7.1 Overview............................................................................................................................7-1

7.1.1 Features................................................................................................................7-2

7.1.2 Pin Descriptions....................................................................................................7-4

7.2 Liquid Crystal Display Controller Operation.......................................................................7-4

7.2.1 Enabling the Controller .........................................................................................7-4

7.2.2 Disabling the Controller ........................................................................................7-5

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Intel PXA26X User Manual Page 6

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