Intel PXA26X User Manual download pdf (Page 346)

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101

9-8 Intel® PXA26x Processor Family Developer’s Manual

Inter-Integrated Circuit Bus Interface Unit

The first byte transmission must be followed by an ACK pulse from the addressed slave. When the

transaction is a write, the I

C unit remains in master-transmit mode and the addressed slave device

stays in slave-receive mode. When the transaction is a read, the I

C unit transitions to master-

receive mode immediately following the ACK and the addressed slave device transitions to slave-

transmit mode. When a NAK is returned, the I

C unit aborts the transaction by automatically

sending a STOP and setting the ISR[BED] bit.

When the I

C unit is enabled and idle, it remains in slave-receive mode and monitors the I

C bus

for a START signal. When it detects a START pulse, the I

C unit reads the first seven bits and

compares them to those in the ISAR and the general call address (0x00). When the bits match those

in the ISAR register, the I

C unit reads the eighth bit (R/nW bit) and transmits an ACK pulse. The

C unit either remains in slave-receive mode (R/nW = 0) or transitions to slave-transmit mode (R/

nW = 1). See Section 9.4.7, “General Call Address” for actions when a general call address is

detected.

9.4.3 Inter-Integrated Circuit Acknowledge

Every I

C byte transfer must be accompanied by an acknowledge pulse that the master- or slave-

receiver must generate. The transmitter must release the SDA line for the receiver to transmit the

acknowledge pulse (see Figure 9-5).

Figure 9-4. Data Format of First Byte in Master Transaction

7-Bit I2C Slave Address

Read/Write Transaction

MSB

LSB

(0) Write

(1) Read

Figure 9-5. Acknowledge on the I

C Bus

2-7

SCL from

Master

Data Output

by Receiver

Data Output

by Transmitter

Clock Pulse

for Acknowledge

SDA released

SDA pulled low

by Receiver (ACK)

Start Condition

∼

(SDA)

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