Intel PXA26X User Manual download pdf (Page 450)

12-40 Intel® PXA26x Processor Family Developer’s Manual

Universal Serial Bus Device Controller

12.6.10 UDC Status/Interrupt Register 0 (USIR0)

The UDC status/interrupt registers (USIR0 and USIR1) contain bits that generate the UDC’s

interrupt request. Each bit in the UDC status/interrupt registers is logically ORed together to

produce one interrupt request. When the ISR for the UDC is executed, it must read the UDC status/

interrupt register to determine why the interrupt occurred. USIRx is level sensitive. Be sure to clear

USIRx as the last step before exiting the ISR.

The bits in USIR0 and USIR1 are controlled by a mask bit in the UDC Interrupt Control Register

(UICR0/1). The mask bits, when set, prevent a status bit in the USIRx from being set. If the mask

bit for a particular status bit is cleared and an interruptible condition occurs, the status bit is set. To

clear status bits, the core must write a 1 to the position to be cleared. The interrupt request for the

UDC remains active as long as the value of the USIRx is non-zero.

12.6.10.1 Endpoint 0 Interrupt Request (IR0)

The endpoint 0 interrupt request is set if the IM0 bit in the UDC control register is cleared and, in

the UDC endpoint 0 control/status register, the OUT packet ready bit is set, the IN packet ready bit

is cleared, or the sent STALL bit is set. The IR0 bit is cleared by writing a 1 to it.

12.6.10.2 Endpoint 1 Interrupt Request (IR1)

The interrupt request bit is set if the IM1 bit in the UDC interrupt control register is cleared and the

IN packet complete (TPC) in UDC endpoint 1 control/status register is set. The IR1 bit is cleared

by writing a 1 to it.

12.6.10.3 Endpoint 2 Interrupt Request (IR2)

The interrupt request bit is set if the IM2 bit in the UDC interrupt control register is cleared and the

OUT packet ready bit (RPC) in the UDC endpoint 2 control/status register is set. The IR2 bit is

cleared by writing a 1 to it.

12.6.10.4 Endpoint 3 Interrupt Request (IR3)

The interrupt request bit is set if the IM3 bit in the UDC interrupt control register is cleared and the

IN packet complete (TPC) or Transmit Underrun (TUR) in UDC endpoint 3 control/status register

is set. The IR3 bit is cleared by writing a 1 to it

12.6.10.5 Endpoint 4 Interrupt Request (IR4)

The interrupt request bit is set if the IM4 bit in the UDC interrupt control register is cleared and the

OUT packet ready (RPC) or receiver overflow (ROF) in the UDC endpoint 4 control/status register

or the Isochronous Error Endpoint 4 (IPE4) in the UFNHR are set. The IR4 bit is cleared by writing

a 1 to it.

12.6.10.6 Endpoint 5 Interrupt Request (IR5)

The interrupt request bit is set if the IM5 bit in the UDC interrupt control register is cleared and the

IN packet complete (TPC) in UDC endpoint 5 control/status register is set. The IR5 bit is cleared

by writing a 1 to it.

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Intel PXA26X User Manual Page 450