Intel PXA26X User Manual download pdf (Page 82)

3-16 Intel® PXA26x Processor Family Developer’s Manual

Clocks and Power Manager

• A power enable input pin that enables the primary supply output connected to VCC and

PLL_VCC. This pin must be connected to the processor’s PWR_EN pin. To support fast sleep

wake up by maintaining power during sleep, the regulator should be software configurable to

ignore PWR_EN. When PWR_EN is not used, VCC and PLL_VCC may be powered on

before or simultaneously with VCCN and VCCQ. In this configuration, when PWR_EN is

deasserted the core regulator must be able to maintain regulation when the load power is as

little as 0.5 mW. Core supply current during sleep varies with voltage and temperature.

• When core power is enabled during sleep, the power management IC or logic that generates

nVDD_FAULT must assert this signal when any supply including VCC and PLL_VCC falls

below the lower-regulation limit during sleep. nVDD_FAULT must not be deasserted until all

supplies are again in regulation since there is no power-supply-stabilization-delay during the

fast-sleep-wake-up sequence. If nVDD_FAULT is asserted during fast-sleep wake up, then the

processor returns to sleep mode.

• When configured to save power during sleep by disabling the supply, drive the core regulator’s

output to ground when PWR_EN goes low.

• Higher-voltage outputs connected to VCCQ and VCCN are continuously driven and do not

change when the PWR_EN pin is asserted.

3.4.9.2 Preparing for Sleep Mode

To prepare for sleep mode, software must:

1. Configure the memory controller to ensure SDRAM contents are maintained during sleep

mode. See Chapter 6, “Memory Controller” for details.

2. If a graceful shutdown is required for a peripheral, disable the peripheral before sleep mode

asserts. This includes monitoring DMA transfers to and from peripherals or memories to

ensure they are completed. All other peripherals need not be disabled, since they are held in

their reset states internally during sleep mode.

3. Set up these power manager (PM) registers for proper sleep entry and exit:

— PM GPIO Sleep State registers (PGSR0, PGSR1, PGSR2). To avoid contention on the bus

when the processor attempts to wake up, ensure that the chip selects are not set to 0 during

sleep mode. If a GPIO is used as an input, it must not be allowed to float during sleep

mode. The GPIO can be pulled up or down externally or changed to an output and driven

with the unasserted value.

— PM General Configuration Register Float bits [FS/FP]. Configure these bits appropriately

for the system. The General Configuration Register Float bits must be cleared on wake up.

To avoid contention on the bus when the processor attempts to wake up, ensure that the

chip selects are not set to 0 during sleep mode. The PCFR[OPDE] bit must be cleared to

leave the 3.6864 MHz enabled during sleep if the fast-wake-up-sleep configuration is

selected using the PMFWR[FWAKE] bit.

— PMFWR configuration register. Set this register to select between the standard and fast-

sleep-wake-up configurations. If power is maintained during sleep, set PMFWR[FWAKE]

to 1 to disable the 10 ms power supply stabilization delay during sleep wake up. This

configuration reduces the sleep wake up time to approximately 650

µs.

4. Before the IDAE bit is set, software must configure an imprecise data abort exception handler

to put the processor into sleep mode. This is necessary when a data abort occurs in response to

nVDD_FAULT or nBATT_FAULT assertion. This abort exception event indicates that the

processor is in peril of losing its main power supply.

5. Set up these power manager registers to detect wake-up sources and oscillator activity:

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 623 624

Comments to this Manuals

No comments

Intel PXA26X User Manual Page 82

Comments to this Manuals

Related products and manuals for Laptops Intel PXA26X