Intel PXA26X User Manual download pdf (Page 509)

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Intel® PXA26x Processor Family Developer’s Manual 14-13

Inter-Integrated Circuit Sound Controller

14.6.4 Serial Audio Clock Divider Register (SADIV)

This register is used for generating six different BITCLK frequencies and hence six different

sampling frequencies. All bits are read/write. Table 14-8 shows the bit layout of SADIV.

The reset value, 0x0000001A, defaults to a sampling frequency of 22.05 KHz.

Note: Setting this register to values other than those shown in Table 14-2, “Supported Sampling

Frequencies” on page 14-6 is not allowed and will cause unpredictable activity.

14.6.5 Serial Audio Interrupt Clear Register (SAICR)

The Serial Audio Interrupt Clear Register (SAICR) is the Interrupt Control Register. This is only an

addressable location and no data is actually stored. These addressable locations are used only for

clearing status register (SASR0) bits. Each bit position corresponds to an interrupt source bit

position in the Status register. Table 14-9 shows the bit layout of SAICR.

This is a write-only register. A read operation will be treated as a read from a reserved location.

The reset value is reserved, since the register cannot be read.

Table 14-8. SADIV Bit Descriptions

Physical Address

0x4040-0060

Serial Audio Clock Divider

S Controller

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved SADIV

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0

Bits Name Description

31:7 — Reserved

6:0 SADIV

Audio clock divider. Valid SADIV(6:0) are:

000 1100 – BITCLK of 3.072 MHz

000 1101 – BITCLK of 2.836 MHz

001 1010 – BITCLK of 1.418 MHz

010 0100 – BITCLK of 1.024 MHz

011 0100 – BITCLK of 708.92 KHz

100 1000 – BITCLK of 512.00 KHz

1 2 ... 504 505 506 507 508 509 510 511 512 513 514 ... 623 624

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Intel PXA26X User Manual Page 509

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