Intel PXA26X User Manual download pdf (Page 403)

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Intel® PXA26x Processor Family Developer’s Manual 11-9

Fast Infrared Communication Port

Table 11-2. Fast Infrared Communication Port Control Register 0 (Sheet 1 of 2)

0x4080 0000

Fast Infrared Communication Port

Control Register 0 (ICCR0)

FICP

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

AME

TIE

RIE

RXE

TXE

TUS

LBM

ITR

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits Name Description

[31:8] — Reserved

7AME

ADDRESS MATCH ENABLE:

Receive logic will compare the address of the incoming frames to the Address Match Value

field in ICCR1.

0 – Disable receiver address match function. Store data in receive FIFO.

1 – Enable receiver address match function. Do not put data in the receive FIFO unless

address is recognized or address is the broadcast address.

6TIE

TRANSMIT FIFO INTERRUPT ENABLE:

0 – Transmit FIFO service request, ICSR0[TFS], does not generate an interrupt.

1 – Transmit FIFO service request generates an interrupt.

Setting TIE does not clear TFS or prevent TFS from being set or cleared by the transmit

FIFO. TIE does not affect transmit FIFO DMA requests.

5RIE

RECEIVE FIFO INTERRUPT ENABLE:

0 – Receive FIFO service request, ICSR0[RFS], does not generate an interrupt.

1 – Receive FIFO service request generates an interrupt

Setting RIE does not clear RFS or prevent RFS from being set or cleared by the receive

FIFO. RIE does not affect receive FIFO DMA requests.

4RXE

RECEIVE ENABLE:

0 – FICP receive logic disabled.

1 – FICP receive logic enabled if ICCR0[ITR] is set.

All other control bits must be configured before setting RXE. If RXE is cleared while

receiving data then reception is stopped immediately, all data within the receive FIFO and

serial input shifter is cleared, and control of the receive data pin is given to the SIU.

While communication is normally half-duplex, it is possible to transmit and receive data at

the same time. This is used for testing in Loopback Mode.

If RXE is used to clear the receive FIFO, check ICSR1[RNE] to ensure the receive FIFO is

clear before re-enabling the receiver.

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