Intel PXA26X User Manual download pdf (Page 508)

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14-12 Intel® PXA26x Processor Family Developer’s Manual

Inter-Integrated Circuit Sound Controller

Table 14-7. SASR0 Bit Descriptions

Physical Address

0x4040-000C

Serial Audio Controller I

S/MSB-

Justified Status Register

S Controller

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RFL TFL

Reserved

ROR

TUR

RFS

TFS

BSY

RNE

TNF

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bits Name Description

31:16 — Reserved

15:12 RFL

RECEIVE FIFO LEVEL:

Number of entries in receive FIFO

11:8 TFL

TRANSMIT FIFO LEVEL:

Number of entries in transmit FIFO

7—Reserved

6ROR

RECEIVE FIFO OVERRUN:

0 – Receive FIFO has not experienced an overrun

1 – I

S attempted data write to full receive FIFO (Interruptible)

Can interrupt processor if bit6 of Serial Audio Interrupt Mask Register is set.

Cleared by setting bit 6 of Serial Audio Interrupt Clear Register.

5TUR

TRANSMIT FIFO UNDER-RUN:

0 – Transmit FIFO has not experienced an under-run

1 – I

S attempted data read from an empty transmit FIFO

Can interrupt processor if bit5 of Serial Audio Interrupt Mask Register is set.

Cleared by setting bit 5 of Serial Audio Interrupt Clear Register.

4RFS

RECEIVE FIFO SERVICE REQUEST:

0 – Receive FIFO level below RFL threshold, or I

S disabled

1 – Receive FIFO level is at or above RFL threshold.

Can interrupt processor if bit 4 of Serial Audio Interrupt Mask Register is set.

Cleared automatically when # of receive FIFO entries < (RFTH + 1).

3 TFS

TRANSMIT FIFO SERVICE REQUEST:

0 – Transmit FIFO level exceeds TFL threshold, or I

S disabled

1 – Transmit FIFO level is at or below TFL threshold

Can interrupt processor if bit 3 of Serial Audio Interrupt Mask Register is set.

Cleared automatically when # of transmit FIFO entries >= (TFTH + 1).

2 BSY

S BUSY:

0 – I

S is idle or disabled

1 – I

S currently transmitting or receiving a frame

1 RNE

RECEIVE FIFO NOT EMPTY:

0 – Receive FIFO is empty

1 – Receive FIFO is not empty

0TNF

TRANSMIT FIFO NOT FULL:

0 – Transmit FIFO is full

1 – Transmit FIFO is not full

1 2 ... 503 504 505 506 507 508 509 510 511 512 513 ... 623 624

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Intel PXA26X User Manual Page 508

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