Intel E3-1275 Datasheet download pdf (Page 81)

Datasheet, Volume 2 81

Processor Configuration Registers

2.5.33 ERRCMD—Error Command Register

This register controls the Host Bridge responses to various system errors. Since the

Host Bridge does not have an SERRB signal, SERR messages are passed from the

processor to the PCH over DMI.

When a bit in this register is set, a SERR message will be generated on DMI whenever

the corresponding flag is set in the ERRSTS register. The actual generation of the SERR

message is globally enabled for Device 0 using the PCI Command register.

2.5.34 SMI Command Register

This register enables various errors to generate an SMI DMI special cycle. When an

error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI

special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,

respectively. Note that one and only one message type can be enabled.

B/D/F/Type: 0/0/0/PCI

Address Offset: CA–CBh

Reset Value: 0000h

Access: RW

Size: 16 bits

BIOS Optimal Default 0000h

Bit Attr

Reset

Value

RST/

PWR

Description

15:2 RO 0h Reserved

1 RW 0b Uncore

SERR Multiple-Bit DRAM ECC Error (DMERR)

1 = The Host Bridge generates an SERR message over DMI when

it detects a multiple-bit error reported by the DRAM controller.

0 = Reporting of this condition using SERR messaging is disabled.

For systems not supporting ECC, this bit must be disabled.

0 RW 0b Uncore

SERR on Single-bit ECC Error (DSERR)

1 = The Host Bridge generates an SERR special cycle over DMI

when the DRAM controller detects a single bit error.

0 = Reporting of this condition using SERR messaging is disabled.

For systems that do not support ECC, this bit must be disabled.

B/D/F/Type: 0/0/0/PCI

Address Offset: CC–CDh

Reset Value: 0000h

Access: RW

Size: 16 bits

BIOS Optimal Default 0000h

Bit Attr

Reset

Value

RST/

PWR

Description

15:2 RO 0h Reserved

1 RW 0b Uncore

SMI on Multiple-Bit DRAM ECC Error (DMESMI)

1 = The Host generates an SMI DMI message when it detects a

multiple-bit error reported by the DRAM controller.

0 = Reporting of this condition using SMI messaging is disabled.

For systems not supporting ECC, this bit must be disabled.

0 RW 0b Uncore

SMI on Single-bit ECC Error (DSESMI)

1 = The Host generates an SMI DMI special cycle when the DRAM

controller detects a single bit error.

0 = Reporting of this condition using SMI messaging is disabled.

For systems that do not support ECC, this bit must be disabled.

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Intel E3-1275 Datasheet Page 81

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