Intel E3-1275 Datasheet download pdf (Page 101)

Datasheet, Volume 2 101

Processor Configuration Registers

2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper

The functionality associated with this register is present in the PEG design

implementation. This register in conjunction with the corresponding Upper Base

Address register controls the processor to PCI Express-G prefetchable memory access

routing based on the following formula:

PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits

A[31:20] of the 39-bit address. The lower 7 bits of the Upper Base Address register are

read/write and correspond to address bits A[38:32] of the 39-bit address. This register

must be initialized by the configuration software. For the purpose of address decode,

address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory

address range will be aligned to a 1 MB boundary.

B/D/F/Type: 0/1/0–2/PCI

Address Offset: 28–2Bh

Reset Value: 0000_0000h

Access: RW

Size: 32 bits

Bit Attr

Reset

Value

RST/

PWR

Description

31:0 RW

0000_000

Uncore

Prefetchable Memory Base Address (PMBASEU)

This field corresponds to A[63:32] of the lower limit of the

prefetchable memory range that will be passed to PCI Express-G.

1 2 ... 96 97 98 99 100 101 102 103 104 105 106 ... 299 300

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Intel E3-1275 Datasheet Page 101