Intel E3-1275 Datasheet Page 260

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Processor Configuration Registers
260 Datasheet, Volume 2
2.19 PCU MCHBAR Registers
Table 2-21 lists the registers arranged by address offset. Register bit descriptions are in
the sections following the table.
Table 2-21. PCU MCHBAR Register Address Map
Register
Start
Register Symbol Register Name Reset Value Access
0–587Fh RSVD Reserved 0h RO
5880–5883
MEM_TRML_ESTI
MATION_CONFIG
Memory Thermal Estimation Configuration
438C_8324h RW
5884–5887 RSVD Reserved 0000_0000h RW
5888–588B
MEM_TRML_THRE
SHOLDS_CONFIG
Memory Thermal Thresholds Configuration
00E4_D5D0h RW
588C–589Fh RSVD Reserved
58A0–58A3
MEM_TRML_STAT
US_REPORT
Memory Thermal Status Report
0000_0000h RO-V
58A4–58A7
MEM_TRML_TEMP
ERATURE_REPORT
Memory Thermal Temperature Report
0000_0000h RO-V
58A8–58AB
MEM_TRML_INTER
RUPT
Memory Thermal Interrupt
0000_0000h RW
58AC–5D0Fh RSVD Reserved
5948-594Bh GT_PERF_STATUS GT Performance Status 0000_0000h RO-V
58AC–5997 RSVD Reserved
5998-599Bh RP_STATE_CAP RP State Capability 0000_0000h RO-FW
599C–5D0Fh RSVD Reserved
5D10–5D17 SSKPD
Sticky Scratchpad Data 0000_0000_
0000_0000h
RWS
5D18–5F0Bh RSVD Reserved
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