Intel E3-1275 Datasheet download pdf (Page 31)

Datasheet, Volume 2 31

Processor Configuration Registers

The Remap window is inclusive of the Base and Limit addresses. In the decoder

A[19:0] of the Remap Base Address are assumed to be 0s. Similarly, A[19:0] of the

Remap Limit Address are assumed to be Fhs. Thus, the bottom of the defined memory

range will be aligned to a megabyte boundary and the top of the defined range will be

one less than a MB boundary.

Setting the Remap Base register to a value greater than that programmed into the

Remap Limit register disables the remap function.

Software Responsibility and Restrictions

• BIOS is responsible for programming the REMAPBASE and REMAPLIMIT registers

based on the values in the TOLUD, TOM, and ME stolen size registers.

• The amount of remapped memory defined by the REMAPBASE and REMAPLIMIT

registers must be equal to the amount of physical memory between the TOLUD

and the lower of either 4 GB or TOM minus the ME stolen size.

• Addresses of MMIO region must not overlap with any part of the Logical Address

Memory Remap range.

• When TOM is equal to TOLUD, remap is not needed and must be disabled by

programming REMAPBASE to a value greater than the value in the REMAPLIMIT

Interaction with other Overlapping Address Space

The following Memory Mapped IO address spaces are all logically addressed below 4 GB

where they do not overlap the logical address of the re-mapped memory region:

GFXGTTstolen At (TOLUD – GFXstolensize) to TOLUD

GFXstolen At ((TOLUD – GFXstolensize) – GFXGTTstolensize) to (TOLUD –

GFXstolensize)

TSEG At ((TOLUD – GFXstolensize – GFXGTTstolensize) – TSEGSIZE) to

(TOLUD – GFXGTTstolensize – GFXstolensize)

High BIOS Reset vector just under 4GB boundary (Positive decode to DMI

occurs)

XAPIC At fixed address below 4 GB

Local APIC At fixed address below 4 GB

MSI Interrupts At fixed address below 4 GB

GMADR 64 bit BARs

GTTMMADR 64 bit BARs MBASE/MLIMIT

PXPEPBAR 39 bit BAR

DMIBAR 39 bit BAR

MCHBAR 39 bit BAR

TMBAR 64 bit BAR

PMBASE/PMLIMIT 64 bit BAR (using Upper PMBASE/PMLIMIT)

CHAPADR 64 bit BAR

GFXVTBAR 39 bit BARs

VTDPVC0BAR 39 bit BARs

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Intel E3-1275 Datasheet Page 31