Intel E3-1275 Datasheet download pdf (Page 220)

Processor Configuration Registers

220 Datasheet, Volume 2

2.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Register

This register defines channel characteristics—number of DIMMs, number of ranks, size,

ECC, interleave options, and ECC options.

B/D/F/Type: 0/0/0/MCHBAR_MCMAIN

Address Offset: 5008–500Bh

Reset Value: 0060_0000h

Access: RW-L

Size: 32 bits

BIOS Optimal Default 00h

Bit Attr

Reset

Value

RST/

PWR

Description

31:26 RO 0h Reserved

25:24 RW-L 00b Uncore

ECC is active in the channel (ECC)

00 = No ECC active in the channel

01 = ECC is active in I/O; ECC logic is not active. In this case, on

write accesses the data driven on ECC byte is copied from

DQ 7:0 (to be used in training or IOSAV)

10 = ECC is disabled in I/O, but ECC logic is enabled (to be used

in ECC4ANA mode)

11 = ECC active in both I/O and ECC logic

23 RO 0h Reserved

22 RW-L 1b Uncore

Enhanced Interleave mode (Enh_Interleave)

0 = Off

1 = On

21 RW-L 1b Uncore

Rank Interleave (RI)

0 = Off

1 = On

20 RW-L 0b Uncore

DIMM B DDR width (DBW)

DIMM B width of DDR chips

0 = X8 chips

1 = X16 chips

19 RW-L 0b Uncore

DIMM A DDR width (DAW)

DIMM A width of DDR chips

0 = X8 chips

1 = X16 chips

18 RW-L 0b Uncore

DIMM B number of ranks (DBNOR)

0 = Single rank

1 = Dual rank

17 RW-L 0b Uncore

DIMM A number of ranks (DANOR)

0 = Single rank

1 = Dual rank

16 RW-L 0b Uncore

DIMM A select (DAS)

Selects which of the DIMMs is DIMM A – should be the larger

DIMM:

0 = DIMM 0

1 = DIMM 1

15:8 RW-L 00h Uncore

Size of DIMM B (DIMM_B_Size)

Size of DIMM B in 256 MB multiples

7:0 RW-L 00h Uncore

Size of DIMM A (DIMM_A_Size)

Size of DIMM A in 256 MB multiples

1 2 ... 215 216 217 218 219 220 221 222 223 224 225 ... 299 300

Comments to this Manuals

No comments

Intel E3-1275 Datasheet Page 220

Comments to this Manuals

Related products and manuals for Processors Intel E3-1275