Intel E3-1275 Datasheet download pdf (Page 207)

Datasheet, Volume 2 207

Processor Configuration Registers

2.13 MCHBAR Registers in Memory Controller –

Channel 0

Table 2-15 lists the registers arranged by address offset. Register bit descriptions are in

the sections following the table.

2.13.1 TC_DBP_C0—Timing of DDR Bin Parameters Register

This register defines the BIN timing parameters for safe logic – tRCD, tRP, and tCL.

Table 2-15. MCHBAR Registers in Memory Controller – Channel 0 Register Address Map

Address

Offset

0–3FFFh RSVD Reserved — —

4000–4003h TC_DBP_C0 Timing of DDR Bin Parameters 0000_0666h RW-L

4004–4007h TC_RAP_C0

Timing of DDR Regular Access

Parameters

0010_4044h RW-L

4028–402Bh SC_IO_LATENCY_C0 IO Latency Configuration 0000_0000h RW-L

42A4–42A7h TC_SRFTP_C0 Self-Refresh Timing Parameters 0000_B000h RW-L

40B0-40B3h PM_PDWN_config_C0 Power-down Configuration 0000_0000h RW-L

40B4–40C7h RSVD Reserved — —

40C8–40CBh ECCERRLOG0_C0 ECC Error Log 0 0000_0000h ROS-V

40CC–40CFh ECCERRLOG1_C0 ECC Error Log 1 0000_0000h ROS-V

40D0–438Fh RSVD Reserved — —

4294–4297h TC_RFP_C0 Refresh Parameters 46B4_1004h RW-L

4298–429Bh TC_RFTP_C0 Refresh Timing Parameters 0000_980Fh RW-L

429C–438Fh RSVD Reserved — —

B/D/F/Type 0/0/0/MCHBAR_MCMAIN

Address Offset: 4000–4003h

Reset Value: 0000_0666h

Access: RW-L

Size: 32 bits

Bit Attr

Reset

Value

RST/

PWR

Description

31:12 RO 0h Reserved

11:8 RW-L 6h

CAS Command Delay to Data Out of DDR Pins (tCL)

This field provides the delay from CAS command to data out of

DDR pins.

Range is 5 – 12.

Notes:

1. This does not define the sample point in the I/O. This is

defined by training in round-trip register and other registers,

because this is also affected by board delays.

7:4 RW-L 6h

PRE to ACT Same Bank Delay (tRP)

Range is 4 – 15 DCLK cycles.

3:0 RW-L 6h

ACT to CAS (RD or WR) Same Bank Delay (tRCD)

Range is 4 – 15.

1 2 ... 202 203 204 205 206 207 208 209 210 211 212 ... 299 300

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Intel E3-1275 Datasheet Page 207

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