Intel E3-1275 Datasheet download pdf (Page 144)

Processor Configuration Registers

144 Datasheet, Volume 2

2.9 Device 2 I/O Registers

2.9.1 INDEX—MMIO Address Register

A 32-bit I/O write to this port loads the offset of the MMIO register or offset into the

GTT that needs to be accessed. An I/O Read returns the current value of this register.

This mechanism to access internal graphics MMIO registers must not be used to access

VGA IO registers which are mapped through the MMIO space. VGA registers must be

accessed directly through the dedicated VGA IO ports.

2.9.2 DATA—MMIO Data Register

A 32-bit I/O write to this port is re-directed to the MMIO register/GTT location pointed

to by the INDEX register. A 32 bit IO read to this port is re-directed to the MMIO

Table 2-11. Device 2 I/O Register Address Map

Address

Offset

Symbol

0–3h Index MMIO Address Register 0000_0000h RW

4–7h Data MMIO Data Register 0000_0000h RW

B/D/F/Type: 0/2/0/PCI IO

Address Offset: 0–3h

Reset Value: 0000_0000h

Access: RW

Size: 32 bits

BIOS Optimal Default 0000_0000h

Bit Attr

Reset

Value

RST/

PWR

Description

31:21 RO 0h Reserved

20:2 RW 00000h

FLR,

Uncore

This field selects any one of the DWORD registers within the MMIO

This field selects a GTT offset if the target is the GTT.

1:0 RW 00b

FLR,

Uncore

Target (TARG)

00 = MMIO Registers

01 = GTT

1X = Reserved

B/D/F/Type: 0/2/0/PCI IO

Address Offset: 4–7h

Reset Value: 0000_0000h

Access: RW

Size: 32 bits

Bit Attr

Reset

Value

RST/

PWR

Description

31:0 RW

0000_000

FLR,

Uncore

MMIO Data Window (DATA)

This field is the data field associated with the IO2MMIO access.

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