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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS
Revision 1.2
Intel order number E39529-009
20
3.1 Intel
®
5520 and 5500 I/O Hub (IOH)
The Intel
®
5520 and 5500 I/O Hub (IOH) in the Intel
®
Server Boards S5520HC and S5500HCV
provide a connection point between various I/O components and Intel
®
QPI-based processors,
which includes the following core platform functions:
– Intel
®
QPI link interface for the processor subsystem
– PCI Express* Ports
– Enterprise South Bridge Interface (ESI) for connecting Intel
®
ICH10R
– Manageability Engine (ME)
– Controller Link (CL)
– SMBus Interface
– Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
The following table shows the high-level features of the Intel
®
5520 and 5500 IOH:
Table 1. IOH High-Level Summary
IOH
SKU
Intel® QPI
Ports
Supported Processor PCI Express*
Lanes
Manageability
5520 2 Intel
®
Xeon
®
Processor 5500 Series 36 Intel
®
Intelligent Power Node
Manager
5500 2 Intel
®
Xeon
®
Processor 5500 Series 24 Intel
®
Intelligent Power Node
Manager
3.1.1 Intel
®
QuickPath Interconnect
The Intel
®
Server Boards S5520HC and S5500HCV provide two full-width, cache-coherent, link-
based Intel
®
QuickPath Interconnect interfaces from Intel
®
5520 and 5500 IOH for connecting
Intel
®
QPI based processors. The two Intel
®
QPI link interfaces support full-width communication
only and have the following main features:
Packetized protocol with 18 data/protocol bits and 2 CRC bits per link per direction
Supporting 4.8 GT/s, 5.86 GT/s, and 6.4 GT/s
Fully-coherent write cache with inbound write combining
Read Current command support
Support for 64-byte cache line size
3.1.2 PCI Express* Ports
The Intel
®
5520 IOH is capable of interfacing with up to 36 PCI Express* Gen2 lanes, which
support devices with the following link width: x16, x8, x4, x2, and x1.
The Intel
®
5500 IOH is capable of interfacing with up to 24 PCI Express* Gen2 lanes, which
support devices with the following link width: x16, x8, x4, x2, and x1.
All ports support PCI Express* Gen1 and Gen2 transfer rates.
- Server Boards S5520HC and 1
- S5500HCV 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 9
- Revision 1.2 10
- List of Tables 11
- 1. Introduction 15
- 2. Overview 16
- Server Board Layout 19
- 3. Functional Architecture 31
- 3.1 Intel 34
- 5520 and 5500 I/O Hub (IOH) 34
- 3.1.5 Controller Link (CL) 35
- 3.2 Processor Support 36
- Revision 1.2 38
- 3.3 Memory Subsystem 40
- 3.3.2 Supported Memory 42
- Configuration 43
- 3.3.5 Memory Interleaving 46
- 3.3.6 Memory Test 47
- 3.3.7 Memory Scrub Engine 47
- 3.3.8 Memory RAS 47
- 3.4 ICH10R 53
- 3.4.2 USB 2.0 Support 56
- 3.5 PCI Subsystem 57
- 3.6 Intel 60
- Accessory) 60
- 3.6.1 SAS RAID Support 61
- 3.8 Serial Ports 65
- 3.9 Floppy Disk Controller 65
- 3.11 Video Support 65
- 3.11.1 Video Modes 66
- 3.11.2 Dual Video 66
- 3.13 ACPI Support 68
- 3.14 Intel 68
- Virtualization Technology 68
- 3.15 Intel 68
- I/O Acceleration Technology 68
- 4. Platform Management 69
- 4.2.3 Media Redirection 72
- 4.2.5 Embedded Web server 74
- 4.3 Platform Control 75
- 4.3.2 Fan Speed Control 76
- Fan Domain 1 System Fan 5 77
- 4.4 Intel 79
- 5. BIOS Setup Utility 81
- 5.3.1 Operation 82
- 5.3.2.1 Main Screen 85
- 5.3.2.2.2 Memory Screen 91
- 5.3.2.2.6 PCI Screen 99
- Revision 1.2 103
- Redirection 105
- Information 107
- 6.2 Power Connectors 120
- 6.3.2 LCP / IPMB Header 122
- 6.3.1 Intel 122
- 6.4 Front Panel Connector 123
- 6.5 I/O Connectors 124
- 6.5.3 SATA Connectors 126
- 6.5.4 SAS Module Slot 126
- 6.5.5 Serial Port Connectors 127
- 6.5.6 USB Connector 127
- 6.6 Fan Headers 129
- 7. Jumper Blocks 131
- 7.1.1 Clearing the CMOS 132
- 7.1.2 Clearing the Password 132
- 7.3 BIOS Recovery Jumper 133
- 8. Intel 135
- Light Guided Diagnostics 135
- 8.2 Fan Fault LED’s 136
- A. System ID LED 137
- B. System Status LED 137
- 8.4 DIMM Fault LEDs 139
- 9.1 Intel 141
- Specifications 141
- 9.2 MTBF 141
- Table 71. MTBF Estimate 142
- 9.4.1 Grounding 145
- 9.4.2 Stand-by Outputs 145
- 9.4.3 Remote Sense 145
- 9.4.4 Voltage Regulation 146
- 9.4.5 Dynamic Loading 146
- 9.4.6 Capacitive Loading 147
- 9.4.7 Ripple / Noise 147
- 9.4.8 Timing Requirements 147
- FCC (USA) 153
- ICES-003 (Canada) 155
- VCCI (Japan) 155
- BSMI (Taiwan) 155
- RRL KCC (Korea) 156
- CNCA (CCC-China) 156
- 10.7 CA Perchlorate Warning 159
- Appendix B: Compatible Intel 162
- Server Chassis 162
- POST Error Beep Codes 185
- Glossary 188
- Reference Documents 192
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