Intel SL2YM Datasheet download pdf (Page 17)

Pentium

II Processor at 350 MHz, 400 MHz, and 450 MHz

Datasheet 17

pull-ups. A resistor of greater than or equal to 10 kΩ may be used to connect the VID signals to the

converter input. Note that no changes have been made to the physical connector between the VRM

8.1 and VRM 8.2 specifications, though pin definitions have changed.

2.7 Processor System Bus Unused Pins

All RESERVED pins must remain unconnected. Connection of these pins to V

CORE

, V

CCL2

, V

, or

to any other signal (including each other) can result in component malfunction or incompatibility

with future Pentium II processors. See Section 5.4 for a pin listing of the processor and the location

of each RESERVED pin.

All TESTHI pins must be connected to 2.5 V via a pull-up resistor of between 1 and 100 kΩ value.

PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to

2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each

PICD line (see Table 2 for recommended values).

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. Unused AGTL+ inputs should be left as no connects; AGTL+ termination is provided

on the processor. Unused active low CMOS inputs should be connected to 2.5 V. Unused active

high inputs should be connected to ground (V

). Unused outputs can be left unconnected. A

resistor must be used when tying bidirectional signals to power or ground. When tying any signal

to power or ground, a resistor will also allow for system testability. For unused pins, it is suggested

that ~10 kΩ resistors be used for pull-ups (except for PICD[1:0] discussed above), and ~1 kΩ

resistors be used as pull-downs.

2.8 Processor System Bus Signal Groups

In order to simplify the following discussion, the Pentium II processor system bus signals have

been combined into groups by buffer type. All Pentium II processor system bus outputs are

open drain and require a high-level source provided externally by the termination or pull-up

resistor.

AGTL+ input signals have differential input buffers, which use V

REF

as a reference signal. AGTL+

output signals require termination to 1.5 V. In this document, the term “AGTL+ Input” refers to the

AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”

refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

EMI pins should be connected to motherboard ground and/or to chassis ground through zero ohm

(0Ω) resistors. The 0Ω resistors should be placed in close proximity to the SC 242 connector. The

path to chassis ground should be short in length and have a low impedance.

The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5 V. The CMOS,

APIC, and TAP outputs are open drain and should be pulled high to 2.5 V. This ensures not only

correct operation for current Pentium II processors, but compatibility for future Pentium II

products as well. See Table 2 for recommended pull-up resistor values on each CMOS signal.

~150Ω resistors are expected on the PICD[1:0] lines; other values in Table 2 are specified for

proper logic analyzer and test mode operation only.

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Intel SL2YM Datasheet Page 17

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