Intel SL2YM Datasheet download pdf (Page 36)

Pentium

II Processor at 350 MHz, 400 MHz, and 450 MHz

36 Datasheet

3.0 S

stem Bus Si

nal Simulations

Signals driven on the Pentium II processor system bus should meet signal quality specifications to

ensure that the components read data properly and to ensure that incoming signals do not affect the

long term reliability of the component. Specifications are provided for simulation at the processor

core; guidelines are provided for correlation to the processor edge fingers. These edge finger

guidelines are intended for use during testing and measurement of system signal integrity.

Violations of these guidelines are permitted, but if they occur, simulation of signal quality at the

processor core should be performed to ensure that no violations of signal quality specifications

occur. Meeting the specifications at the processor core in Table 21, Table 23, and Table 25 ensures

that signal quality effects will not adversely affect processor operation, but does not necessarily

guarantee that the guidelines in Table 22, Table 24, and Table 26 will be met.

Figure 11. Test Timings (TAP Connection)

Figure 12. Test Reset Timings

TCK

DI, TMS

Input

Signals

TDO

Output

Signals

PCB766a

1.25V

T43 (All Non-Test Inputs Setup Time)=

T44 (All Non-Test Inputs Hold Time)=

T40 (TDO Float Delay)=

T37 (TDI, TMS Setup Time)=

T38 (TDI, TMS Hold Time)=

T39 (TDO Valid Delay)=

T41 (All Non-Test Outputs Valid Delay)=

T42 (All Non-Test Outputs Float Delay)=

TRST#

PCB

773

1.25V

T37 (TRST# Pulse Width)=

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 83 84

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Intel SL2YM Datasheet Page 36