Intel SL2YM Datasheet download pdf (Page 38)

Pentium

II Processor at 350 MHz, 400 MHz, and 450 MHz

38 Datasheet

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium

II processor frequencies and cache sizes.

2. This is the Pentium II processor system bus clock overshoot and undershoot measurement guideline.

3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute voltage

the BCLK signal may dip back to after passing the V

(rising) or V

(falling) voltage limits. This guideline is an

absolute value.

4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The midpoint

voltage level of this ledge should be within the range of the guideline.

5. The ledge (V7’) is allowed to have peak-to-peak oscillation as given in the guideline.

3.2 AGTL+ Signal Quality Specifications and Measurement

Guidelines

Many scenarios have been simulated to generate a set of GTL+ layout guidelines which are

available in AP-827, 100 MHz GTL+ Layout Guidelines for the Pentium

II Processor and Intel

440BX AGPset (Order Number 243735). Refer to the Pentium

II Processor Developer's Manual

(Order Number 243502) for the GTL+ buffer specification.

Table 22. BCLK Signal Quality Guidelines for Edge Finger Measurement

T# Parameter Min Nom Max Unit Fi

ure Notes

V1’: BCLK V

0.5 V 14

V2’: BCLK V

2.0 V 14

V3’: V

Absolute Voltage Range –0.5 3.3 V 14 2

V4’: Rising Edge Ringback 2.0 V 14 3

V5’: Falling Edge Ringback 0.5 V 14 3

V6’: T

line

Ledge Voltage 1.0 1.7 V 14 At Ledge Midpoint

V7’: T

line

Ledge Oscillation 0.2 V 14 Peak-to-Peak

Figure 14. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers

000808

T6 T4 T5

Time

Voltage

’

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 83 84

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