Intel SL2YM Datasheet download pdf (Page 27)

Pentium

II Processor at 350 MHz, 400 MHz, and 450 MHz

Datasheet 27

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium

II processor frequencies and cache sizes.

2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core pin. All

AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core pins.

3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core pin. All

CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.

4. The internal core clock frequency is derived from the Pentium II processor system bus clock. The system bus clock to

core clock ratio is determined during initialization as described in Section 2.5. Table 11 shows the supported ratios for

each processor.

5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.

6. This specification applies to the Pentium II processor when operating with a Pentium II processor system bus frequency

of 100 MHz.

7. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be used that

is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be measured on the

risin

es of ad

acent BCLKs crossin

1.25 V at the

rocessor core

. The jitter present must be accounted for

as a component of BCLK timing skew between devices.

8. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created

by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should be less than

500 kHz. This

specification may be ensured by design characterization and/or measured with a spectrum analyzer.

9. Not 100% tested. Specified by design characterization as a clock driver requirement.

10.The average period over a 1uS period of time must be greater than the minimum specified period.

NOTES:

1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency multipliers.

2. While other bus ratios are defined, operation at frequencies other than those listed are not supported.

Table 10. System Bus AC Specifications (Clock) at Processor Core Pins

1, 2, 3

T# Parameter Min Nom Max Unit Fi

ure Notes

System Bus Frequency 100.00 MHz

All processor core

frequencies

T1: BCLK Period 10.0 ns 6 4, 5, 6, 10

T2: BCLK Period Stability ±250 ps 6 6, 7, 8, 10

T3: BCLK High Time 2.6 ns 6 @>2.0 V

T4: BCLK Low Time 2.47 ns 6 @<0.5 V

T5: BCLK Rise Time 0.38 1.25 ns 6 (0.5 V–2.0 V)

6, 9

T6: BCLK Fall Time 0.38 1.5 ns 6 (2.0 V–0.5 V)

6, 9

Table 11. Valid System Bus, Core Frequency, and Cache Bus Frequencies

1, 2

Core Fre

uenc

(MHz) BCLK Fre

uenc

(MHz) Fre

uenc

Multi

lier L2 Cache (MHz)

350.00 100.00 7/2 175.00

400.00 100.00 4/1 200.00

450.00 100.00 9/2 225.00

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