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Datasheet, Volume 2 305
Processor Configuration Registers
9RO 0b
Secondary Discard Timer (SDT)
Not Applicable or Implemented. Hardwired to 0.
8RO 0b
Primary Discard Timer (PDT)
Not Applicable or Implemented. Hardwired to 0.
7RO 0b
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hardwired to 0.
6RW 0b
Secondary Bus Reset (SRESET)
Setting this bit triggers a hot reset on the corresponding PCI Express Port.
This will force the LTSSM to transition to the Hot Reset state (using Recovery)
from L0, L0s, or L1 states.
5RO 0b
Master Abort Mode (MAMODE)
Does not apply to PCI Express. Hardwired to 0.
4RW 0b
VGA 16-bit Decode (VGA16D)
Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address
precluding the decoding of alias addresses every 1 KB. This bit only has
meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling VGA
I/O decoding and forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
3RW 0b
VGA Enable (VGAEN)
This bit controls the routing of processor initiated transactions targeting VGA
compatible I/O and memory address ranges. See the VGAEN/MDAP table in
device 0, offset 97h[0].
2RW 0b
ISA Enable (ISAEN)
Needed to exclude legacy resource decode to route ISA resources to legacy
decode path. Modifies the response by the GMCH to an I/O access issued by
the processor that target ISA I/O addresses. This applies only to I/O
addresses that are enabled by the IOBASE and IOLIMIT registers.
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express-G.
1 = GMCH will not forward to PCI Express-G any I/O transactions addressing
the last 768 bytes in each 1 KB block even if the addresses are within
the range defined by the IOBASE and IOLIMIT registers.
1RW 0b
SERR Enable (SERREN)
0 = No forwarding of error messages from secondary side to primary side
that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
0RW 0b
Parity Error Response Enable (PEREN)
This bit controls whether or not the Master Data Parity Error bit in the
Secondary Status register is set when the MCH receives across the link
(upstream) a Read Data Completion Poisoned TLP.
0 = Master Data Parity Error bit in Secondary Status register can NOT be
set..
1 = Master Data Parity Error bit in Secondary Status register CAN be set.
B/D/F/Type: 0/6/0/PCI
Address Offset: 3E–3Fh
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
- Datasheet – Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Datasheet, Volume 2 11 11
- Revision History 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.2.1 Legacy Address Range 19
- Datasheet, Volume 2 21 21
- 2.2.2.2 TSEG 22
- 2.2.2.5 Pre-allocated Memory 23
- 2.2.2.7 Intel 24
- Management Engine (Intel 24
- ME) UMA 24
- Datasheet, Volume 2 25 25
- 2.2.2.10 High BIOS Area 26
- Datasheet, Volume 2 27 27
- 2.2.3.1 Programming Model 28
- HOST/SYSTEM VIEW 29
- PHYSICAL MEMORY 29
- (DRAM CONTROLLER VIEW) 29
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.2.9 I/O Address Space 35
- 36 Datasheet, Volume 2 36
- Datasheet, Volume 2 37 37
- 2.4 Configuration Mechanisms 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.6 I/O Mapped Registers 44
- 2.7.6 CC—Class Code Register 49
- TXT Lockable 54
- 1:0 to 11b 56
- 4) from 58
- B0h, bits 15:4) 58
- 2.8 MCHBAR Registers 66
- 00h RW 67
- Register Symbol Register Name 67
- 208–209h 73
- 20A–20Bh 74
- 24D–24Fh 74
- 250-251h 75
- 252–255h 76
- 256–257h 77
- 258–25Ah 77
- 269–26Eh 79
- 298–29Bh 82
- 29C–29Fh 84
- 2B4–2B7h 84
- 600–601h 86
- 602–603h 86
- 604–605h 86
- 64D–64Fh 88
- 650–651h 88
- 652–655h 89
- 656–657h 90
- 658–65Ah 90
- 660–663h 91
- 6B4–6B7h 93
- C20–C27h 94
- 1001–1002h 94
- 1004–1005h 95
- 101E–101Fh 100
- Register 107
- 10EC–10EDh 108
- 2C20–2C22h 109
- 2.9 EPBAR Registers 110
- 2.10 PCI Device 1 Registers 115
- PCI device 117
- Port Command Register 140
- 11:10 RW-O 11b 143
- OS's during run time 155
- 104–107h 156
- 108–10Bh 157
- 10C–10Dh 157
- 110–113h 158
- 23 RO 0b Reserved 158
- 114–117h 158
- 11A–11Bh 159
- 2.12 DMIBAR Registers 161
- Declaration Capability 169
- 2.13.6 CC—Class Code Register 177
- Range Address Register 179
- GMADR register 180
- 2.14 Device 2 I/O Registers 183
- 100–107h 211
- 108–10Fh 212
- 200–20Fh 214
- F00–F03h 215
- F04–F07h 216
- Dedication 217
- F08–F0Bh 218
- FFC–FFFh 219
- 2.16 DMI VC1 REMAP Registers 221
- 2.17.2 GFXPLL1—GFX PLL BIOS 254
- 2.18 GFXVTBAR Registers 255
- Address Register 281
- 2.19 PCI Device 6 Registers 288
- 2.19.45 RSTS—Root Status 327
- 2.21 Intel 332
- Specific Registers 332
- 110–117h 333
- 330–337h 333
- Lower Half Register 334
- Upper Half Register 334
- QuickPath Architecture 335
- System Address Decode 335
- Register Description 335
- QPI Link 0 Registers 340
- QPI Physical 0 Registers 341
- 3.4 PCI Standard Registers 342
- 3.4.4 CCR—Class Code Register 344
- Identification Register 345
- 3.4.7 PCICMD—Command Register 346
- 3.5.1 MAX_RTIDS 349
- 3.6.1 SAD_PAM0123 349
- 3.6.2 SAD_PAM456 351
- 3.6.3 SAD_HEN 352
- 3.6.4 SAD_SMRAM 353
- 3.6.5 SAD_PCIEXBAR 354
- 3.7 Intel 356
- QPI Link Registers 356
- 3.8 Intel 357
- QPI Physical Layer Registers 357
- 360 Datasheet, Volume 2 360
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ROSENLEW RMK623 230V manuals
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Table of contents
Tuuletin
7
Tärkeää!
11
0.00 0.30
12
PUHDISTUS
21
VAROITUS!
23
Kaatumiseste
24
Hävittäminen
25
Säkerhet
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Rengöring
32
Kylfläkten
35
Luckspärren
35
VARNING!
36
VIKTIGT!
39
°C Falsläge
41
Stektabell
42
Installation
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