Intel CW8064701487007 Datasheet Page 99

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Datasheet, Volume 1 99
Electrical Specifications
7.4 System Agent (SA) Vcc VID
The V
CCSA
is configured by the processor output pins VCCSA_VID[1:0].
VCCSA_VID[0] output default logic state is low for 2nd Generation Intel
®
Core
®
family
mobile processors.
Note: During boot, the processor V
CCSA
voltage is 0.9 V. The V
CCSA
may change only once
during the reset sequence.
Note: For Ultra products, for power optimization purposes, the VCCSA_VID may change
dynamically during the processor’s operation.
Table 7-2 specifies the different VCCSA_VID configurations.
7.5 Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
RSVD – these signals should not be connected.
RSVD_TP – these signals should be routed to a test point.
RSVD_NCTF – these signals are non-critical to function and may be left un-
connected.
Arbitrary connection of these signals to V
CC
, V
CCIO
, V
DDQ
, V
CCPLL
, V
CCSA,
V
AXG
, V
SS
, or
to any other signal (including each other) may result in component malfunction or
incompatibility with future processors. See Chapter 8 for a pin listing of the processor
and the location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
SS
). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
Table 7-2. VCCSA_VID Configuration
VCCSA_VID[0] VCCSA_VID[1]
Selected V
CCSA
(XE & SV
segments)
Selected V
CCSA
(Ultra segment)
0 0 0.9 V 0.9 V
0 1 0.8 V 0.85 V
1 0 0.725 V 0.775 V
1 1 0.675 V 0.75 V
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