Intel CW8064701487007 Datasheet download pdf (Page 33)

Datasheet, Volume 1 33

Interfaces

2.2.3 PCI Express* Graphics

The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port. The

PEG port is being designed to be compliant with the PCI Express Base Specification,

Revision 3.0.

2.2.3.1 PCI Express* Lanes Connection

Figure 2-5 demonstrates the PCIe lanes mapping.

Figure 2-5. PCI Express* Typical Operation 16 Lanes Mapping

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 171 172

Datasheet – Volume 1 of 2 1
2 Datasheet, Volume 1 2
Contents 3
4 Datasheet, Volume 1 4
Datasheet, Volume 1 5 5
6 Datasheet, Volume 1 6
Datasheet, Volume 1 7 7
8 Datasheet, Volume 1 8
Revision History 9
10 Datasheet, Volume 1 10
1 Introduction 11
Introduction 12
12 Datasheet, Volume 1 12
1.1 Processor Feature Details 13
1.2 Interfaces 13
1.2.2 PCI Express* 14
Datasheet, Volume 1 15 15
1.2.5 Processor Graphics 16
1.3 Power Management Support 17
1.5 Package 19
1.6 Processor Compatibility 20
1.7 Terminology 21
1.8 Related Documents 24
2 Interfaces 25
2.1.3.1 Single-Channel Mode 27
Flex Memory Technology Mode 27
Interfaces 28
28 Datasheet, Volume 1 28
2.1.5.2 Command Overlap 29
2.2 PCI Express* Interface 30
2.2.1.1 Transaction Layer 31
2.2.1.2 Data Link Layer 31
2.2.1.3 Physical Layer 31
32 Datasheet, Volume 1 32
2.2.3 PCI Express* Graphics 33
2.3.1 DMI Error Flow 34
2.3.3 DMI Link Down 34
Datasheet, Volume 1 35 35
2.4.1.2 3D Pipeline 36
2.4.1.3 Video Engine 36
2.4.1.4 2D Engine 37
2.4.2.1 Display Planes 38
2.4.3 Intel 39
2.6 Interface Clocking 40
3 Technologies 41
Technologies 42
42 Datasheet, Volume 1 42
Datasheet, Volume 1 43 43
44 Datasheet, Volume 1 44
3.4 Intel 45
Turbo Boost Technology 45
3.5 Intel 46
3.7 Intel 47
64 Architecture x2APIC 47
48 Datasheet, Volume 1 48
Datasheet, Volume 1 49 49
50 Datasheet, Volume 1 50
4 Power Management 51
(ACPI) States Supported 52
4.2.1 Enhanced Intel 54
SpeedStep 54
Technology 54
4.2.2 Low-Power Idle States 55
4.2.4 Core C-states 57
4.2.5 Package C-States 58
4.2.5.1 Package C0 60
4.2.5.2 Package C1/C1E 60
4.2.5.3 Package C3 State 60
4.2.5.4 Package C6 State 60
Management 61
Power Management 62
62 Datasheet, Volume 1 62
Datasheet, Volume 1 63 63
4.5 DMI Power Management 65
4.6 Graphics Power Management 65
66 Datasheet, Volume 1 66
Datasheet, Volume 1 67 67
68 Datasheet, Volume 1 68
5 Thermal Management 69
5.2 Intel 70
5.3 Intel 70
Table 5-1. Intel 71
Low Power Mode (LPM) 72
5.4.2 Low Power Mode 73
5.6.1.1 TCC Activation Offset 78
Datasheet, Volume 1 79 79
Thermal Management 79
5.6.2 Digital Thermal Sensor 80
5.6.3 PROCHOT# Signal 81
82 Datasheet, Volume 1 82
5.6.4 On-Demand Mode 83
84 Datasheet, Volume 1 84
6 Signal Description 85
Table 6-8. Intel 89
Flexible Display (Intel 89
6.11 Power Sequencing Signals 92
6.12 Processor Power Signals 93
6.13 Sense Signals 93
7 Electrical Specifications 95
7.4 System Agent (SA) Vcc VID 99
7.6 Signal Groups 100
(Prior to Board Attach) 102
7.9 DC Specifications 103
Table 7-5. Processor Core (V 104
Table 7-9. Processor PLL (V 106
DC Specifications 110
Electrical Specifications 112
112 Datasheet, Volume 1 112
8 Processor Pin, Signal, and 113
Datasheet, Volume 1 125 125
126 Datasheet, Volume 1 126
144 Datasheet, Volume 1 144
Datasheet, Volume 1 145 145
160 Datasheet, Volume 1 160
Datasheet, Volume 1 161 161
162 Datasheet, Volume 1 162
Datasheet, Volume 1 163 163
164 Datasheet, Volume 1 164
Datasheet, Volume 1 165 165
166 Datasheet, Volume 1 166
Datasheet, Volume 1 167 167
168 Datasheet, Volume 1 168
9 DDR Data Swizzling 169
Table – Channel A 170
DDR Data Swizzling 172
172 Datasheet, Volume 1 172

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