Intel CW8064701487007 Datasheet download pdf (Page 30)

Interfaces

30 Datasheet, Volume 1

2.1.8 DDR3 Reference Voltage Generation

The processor memory controller has the capability of generating the DDR3 Reference

Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The

generated VREF can be changed in small steps, and an optimum VREF value is

determined for both during a cold boot through advanced DDR3 training procedures in

order to provide the best voltage and signal margins.

2.2 PCI Express* Interface

This section describes the PCI Express interface capabilities of the processor. See the

PCI Express Base Specification for details of PCI Express.

The processor has one PCI Express controller that can support one external x16 PCI

Express Graphics Device. The primary PCI Express Graphics port is referred to as

PEG 0.

2.2.1 PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing

applications and drivers may operate unchanged.

The PCI Express configuration uses standard mechanisms as defined in the PCI

Plug-and-Play specification. The processor external graphics ports support Gen 3 speed

as well. At 8 GT/s, Gen 3 operation results in twice as much bandwidth per lane as

compared to Gen 2 operation. The 16-lane PCI Express* graphics port can operate at

either 2.5 GT/s, 5 GT/s, or 8 GT/s.

PCI Express* Gen 3 uses a 128/130b encoding scheme, eliminating nearly all of the

overhead of the 8b/10b encoding scheme used in Gen 1 and Gen 2 operation.

The PCI Express architecture is specified in three layers – Transaction Layer, Data Link

Layer, and Physical Layer. The partitioning in the component is not necessarily along

these same boundaries. Refer to Figure 2-2 for the PCI Express layering diagram.

Figure 2-2. PCI Express* Layering Diagram

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Intel CW8064701487007 Datasheet Page 30