Intel SDS2 User Manual download pdf (Page 84)

Clock/Voltage Generation and Distribution Intel® Server Board SDS2

Revision 1.2

Order Number: A85874-002

7. Clock/Voltage Generation and Distribution

7.1 Clock

All buses on the SDS2 Server Board operate using synchronous clocks. Clock

synthesizer/driver circuitry on the Server Board generates clock frequencies and voltage levels

as required, including the following:

• 133 MHz at 2.5 V logic levels: For CPU1, CPU2, HE-SL, DIMM Sockets and the ITP port

• 66 MHz at 3.3 V logic levels: For HE-SL, CIOB, P64-B and P64-C PCI slots

• 48 MHz at 3.3V logic levels: For CSB5’s USB

• 33.3 MHz at 3.3 V logic levels: For CIOB, CSB5 and on-board PCI devices and slots

• 16.67 MHz at 2.5 V logic levels: For processor and the CSB5 APIC bus clocks

• 14.318 MHz at 3.3V logic levels: For CSB5 and Video

Other clock sources on the SDS2 Server Board generates:

• 80 MHz at 3.3 V logic levels: For Ultra 360 SCSI Controller

• 32.768 MHz at 3.3 V logic levels: For SIO and BMC

• 14.318 MHz at 3.3 V logic levels: for main clock generator

For information on processor clock generation, see the CK133-WS Synthesizer/Driver

Specification.

The following figure illustrates clock generation and distribution on SDS2 Server Board.

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Intel SDS2 User Manual Page 84