Intel SDS2 User Manual download pdf (Page 31)

Intel® Server Board SDS2 I/O Subsystem

Revision 1.2

Order Number: A85874-002

• The scatter / gather mechanism supports both DMA and PIO IDE drives and ATAPI

devices

• Support for ATA and ATAPI, PIO Mode 0, 1, 2, 3, 4, DMA Mode 0, 1, 2, and Ultra DMA

Mode 0, 1, 2, 3, 4, 5

• The IDE drive transfer rate is capable of up to ATA-100 (100 MB/sec per channel)

4.5.3 USB Interface

The CSB5 contains a USB controller and four USB hubs. The USB controller moves data

between main memory and the four USB connectors.

The SDS2 Server Board provides a three external USB connector interface on the rear I/O. One

additional USB is supported internally through a 10-pin header (2 X 5) that can be cabled to a

front panel board. All four ports function identically and with the same bandwidth. The USB

Specification, Revision 1.1, defines the external connector. Table 68. 10-pin USB Connection

Header (2 x 5) Pin-out.

4.5.4 Compatibility Interrupt Control

The CSB5 provides the functionality of two 82C59 PIC devices for ISA-compatible interrupt

handling.

4.5.5 APIC

The CSB5 integrates a 32-entry I/O APIC that is used to distribute 32 PCI interrupts. It also

includes an additional 16-entry I/O APIC for the distribution of legacy ISA interrupts.

4.5.6 Power Management

One of the embedded functions of CSB5 is a power management controller. The SDS2 Server

Board uses this to implement ACPI-compliant power management features. The SDS2 supports

sleep states S0, S1, S4, and S5.

4.5.7 General Purpose Input and Output Pins

The CSB5 provides a number of general purpose input and output pins. Many of these pins have

alternate functions, and thus all are not available. The following table lists the GPI and GPO pins

used on the SDS2 Server Board and gives a brief description of their function.

Table 10. CSB5 GPIO Usage Table

Pad GPIO Name Description

V3 N_SALERTN Reporting for Fata Errors from HE-SL such as multi-bit ECC errors, Bus

protocol errors, and FSBus parity errors

W2 MIRQL Reporting for Correctable Errors from HE-SL such as single-bit errors on Front

Side Data bus and Memory Data bus

W3 N_CIOBALERTN Reporting for errors from CIOB

Y4 N_CSB5_NMI Generation of NMI from CSB5

Y1 N_BMC_IRQ_SMI_00 Input from BMC of SMI event

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 144 145

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Intel SDS2 User Manual Page 31