Intel SDS2 User Manual Page 21
- Page / 145
- Table of contents
- BOOKMARKS
- Intel® Server Board SDS2 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 10
- List of Tables 11
- 1. Introduction 15
- 2. Architecture 16
- 3. Processor and Chipset 18
- 3.2 Memory Subsystem 20
- DIMM Pair 1 21
- DIMM Pair 2 21
- DIMM Pair 3 21
- 3.3 Chipset 22
- 3.3.3 CSB5 South Bridge 24
- 4. I/O Subsystem 25
- 4.2 Ultra160 SCSI 28
- 4.3 Video Controller 28
- 4.5.1 PCI Bus Interface 30
- 4.5.3 USB Interface 31
- 4.5.5 APIC 31
- 4.5.6 Power Management 31
- 4.6.1 Super I/O 32
- 4.7 Interrupt Routing 34
- 4.7.4 IRQ Scan for PCIIRQ 35
- Serialized IRQ Interface 37
- PCI IRQ Serializer 37
- CSB5 Interrupt Routing 37
- 5. Server Management 39
- 5.2 System Reset Control 44
- 5.4 Error Reporting 46
- 5.5 ACPI 47
- 5.6 AC Link Mode 47
- 6. BIOS 49
- 6.2 BIOS Error Handling 50
- 6.2.3 SMI Handler 52
- 6.2.4 Firmware (BMC) 53
- Table 30. BMC Beep Codes 65
- 6.3 Setup Utility 66
- 6.4 Flash Update Utility 81
- 6.4.2 User Binary Area 82
- 6.4.3 Language Area 82
- 6.4.4 OEM Logo Screen 82
- 6.4.5 Recovery Mode 82
- 7.1 Clock 84
- CPU 1 CPU 2 HE-SL 85
- 7.2 Voltage 86
- Power Supply 87
- 8. Connections 88
- 8.2 Memory Module Connector 89
- 8.3.1 ICMB Connector 90
- 8.3.2 OEM IPMB Connector 90
- 8.4 Front Panel Header 91
- 8.5 PCI Slot Connector 92
- 8.6 I/O Connectors 94
- 8.6.3 NIC Connectors 95
- 8.6.4 IDE Connector 96
- 8.6.6 Floppy Connector 97
- 8.6.7 Serial Port Connector 98
- 8.6.8 Parallel Port 99
- 8.7 Miscellaneous Headers 100
- 8.8 Rear I/O Panel 101
- 9. Jumpers 102
- Revision 1.2 103
- Order Number: A85874-002 103
- Revision 1.2 104
- 9.2.1 Performing CMOS Clear 106
- 10.2 Power Consumption 108
- 10.3.1 Power Timing 109
- 12.1 Regulatory Compliance 113
- 12.2.1 Ensure EMC 114
- SCB2, SDS2 116
- Keyed RJ45 (Type B) 116
- 13. Errata Listing 117
- Adaptor 2100S in Slot 6 134
- S option 137
- Status: Will not fix 137
- Glossary 138
- Reference Documents 140
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