Intel SDS2 User Manual Page 32
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I/O Subsystem Intel® Server Board SDS2
Revision 1.2
Order Number: A85874-002
18
Pad GPIO Name Description
Y19 N_NVRAMCLR Input from jumper to be in BIOS Recovery mode in case of corruption
V17 N_PASSDIS_00 Input from jumper to clear password assignments
U16 N_CMOSCLR_00 Input from jumper to clear setup info in CMOS
T20 N_F3SETUPEN_00 Input from jumper to to be in special test mode (manufacturing only)
T19 N_BMC_SCIN Input from BMC of SCI event
T18 N_BMCISPMD_00 Input from jumper to to be in special test mode (manufacturing only)
U18 N_FRB3STP_00 Output signal to turn off FRB timer to stop fault conditions (this signal is wire-or
with the 2-pin jumper
Y16 N_SCSI_IDSEL_EN Output signal to disable onboard SCSI controller
V12 N_LAN2_IDSEL_EN Output signal to disable onboard NIC2
U12 N_LAN1_IDSEL_EN Output signal to disable onboard NIC1
V19 CSBPICD0 CSB5 APIC Data Bus 0
W20 CSBPICD1 CSB5 APIC Data Bus 1
Y20 N_ROM_CSN Output signal for BIOS Chip Select
U19 N_VGA_IDSEL_EN Output signal to disable onboard Video
4.6 Chipset Support Components
4.6.1 Super I/O
The National Semiconductor PC87417 Super I/O device contains all of the necessary circuitry to
control two serial ports, one parallel port, floppy disk, and PS/2-compatible keyboard and mouse.
The SDS2 Server Board supports the following features:
• GPIO
• Two serial ports
• Floppy
• Keyboard and mouse through PS/2 connectors
• Parallel port
• Real-time clock
• Wake-up control
4.6.1.1 General Purpose Input and Output - GPIO
The National Semiconductor* PC87417 Super I/O provides number of general-purpose
input/output pins that the SDS2 Server Board utilizes. The following table identifies the pin, the
signal name used in the schematic and a brief description of its usage.
Table 11. Super I/O GPIO Usage Table
Pin #
Signal Name Description
10 N_BMC_SYSIRQ_00 System Interrupt Controller interrupt from BMC
13 N_SIO_CLK_40M_BMC 40MHz clock output to BMC
- Intel® Server Board SDS2 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 10
- List of Tables 11
- 1. Introduction 15
- 2. Architecture 16
- 3. Processor and Chipset 18
- 3.2 Memory Subsystem 20
- DIMM Pair 1 21
- DIMM Pair 2 21
- DIMM Pair 3 21
- 3.3 Chipset 22
- 3.3.3 CSB5 South Bridge 24
- 4. I/O Subsystem 25
- 4.2 Ultra160 SCSI 28
- 4.3 Video Controller 28
- 4.5.1 PCI Bus Interface 30
- 4.5.3 USB Interface 31
- 4.5.5 APIC 31
- 4.5.6 Power Management 31
- 4.6.1 Super I/O 32
- 4.7 Interrupt Routing 34
- 4.7.4 IRQ Scan for PCIIRQ 35
- Serialized IRQ Interface 37
- PCI IRQ Serializer 37
- CSB5 Interrupt Routing 37
- 5. Server Management 39
- 5.2 System Reset Control 44
- 5.4 Error Reporting 46
- 5.5 ACPI 47
- 5.6 AC Link Mode 47
- 6. BIOS 49
- 6.2 BIOS Error Handling 50
- 6.2.3 SMI Handler 52
- 6.2.4 Firmware (BMC) 53
- Table 30. BMC Beep Codes 65
- 6.3 Setup Utility 66
- 6.4 Flash Update Utility 81
- 6.4.2 User Binary Area 82
- 6.4.3 Language Area 82
- 6.4.4 OEM Logo Screen 82
- 6.4.5 Recovery Mode 82
- 7.1 Clock 84
- CPU 1 CPU 2 HE-SL 85
- 7.2 Voltage 86
- Power Supply 87
- 8. Connections 88
- 8.2 Memory Module Connector 89
- 8.3.1 ICMB Connector 90
- 8.3.2 OEM IPMB Connector 90
- 8.4 Front Panel Header 91
- 8.5 PCI Slot Connector 92
- 8.6 I/O Connectors 94
- 8.6.3 NIC Connectors 95
- 8.6.4 IDE Connector 96
- 8.6.6 Floppy Connector 97
- 8.6.7 Serial Port Connector 98
- 8.6.8 Parallel Port 99
- 8.7 Miscellaneous Headers 100
- 8.8 Rear I/O Panel 101
- 9. Jumpers 102
- Revision 1.2 103
- Order Number: A85874-002 103
- Revision 1.2 104
- 9.2.1 Performing CMOS Clear 106
- 10.2 Power Consumption 108
- 10.3.1 Power Timing 109
- 12.1 Regulatory Compliance 113
- 12.2.1 Ensure EMC 114
- SCB2, SDS2 116
- Keyed RJ45 (Type B) 116
- 13. Errata Listing 117
- Adaptor 2100S in Slot 6 134
- S option 137
- Status: Will not fix 137
- Glossary 138
- Reference Documents 140
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