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Intel® Server Board S1200BT TPS Platform Management
Revision 1.0
Intel order number G13326-003
41
A list of data that may be captured using this feature includes but is not limited to:
1. Platform sensor readings – This includes all ―readable‖ sensors that can be accessed
by the Integrated BMC firmware and have associated SDRs populated in the SDR
repository.
This does not include any ―event-only‖ sensors.
(All BIOS sensors and some
Integrated BMC and ME sensors are ―event-only‖; meaning that they are not readable
using an IPMI Get Sensor Reading command but rather are used just for event logging
purposes).
2. SEL – The current SEL contents are saved in both hexadecimal and text format.
3. CPU/memory register data useful for diagnosing the cause of the following
system errors:
CATERR, ERR[2], SMI timeout, PERR, and SERR.
The debug data is
saved and timestamped for the last 3 occurrences of the error conditions.
a. PCI error registers
b. MSR registers
c. MCH registers
4. Integrated BMC configuration data
5. Integrated BMC firmware debug log (a.k.a. SysLog) – Captures firmware debug
messages.
4.2.6 Data Center Management Interface (DCMI)
DCMI is an IPMI-based standard that builds upon a set of required IPMI standard commands by
adding a set of DCMI-specific IPMI OEM commands. BTP1200-LC platform will support DCMI
1.0 specification.
4.2.7 Local Directory Authentication Protocol (LDAP)
The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the
Integrated BMC for the purpose of authentication and authorization.
The Integrated BMC user
connects with an LDAP server for login authentication.
This is only supported for non-IPMI
logins including the embedded web UI and SM-CLP. IPMI users/passwords and sessions are
not supported over LDAP.
LDAP can be configured (IP address of LDAP server, port, etc.) via the Integrated BMC‘s
Embedded Web UI. LDAP authentication and authorization is supported over the any NIC
configured for system management. The BMC uses a standard Open LDAP implementation
for Linux.
4.3 Thermal Control
4.3.1 Memory Thermal Throttling
The system shall support thermal management through open loop throttling (OLTT) or static
closed loop throttling (CLTT) of system memory based on availability of valid temperature
- Server Board S1200BT 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 8
- List of Tables 10
- Revision 1.0 11
- 1. Introduction 13
- 2. Overview 14
- 2.2 Server Board Layout 16
- 2.2.2 Intel 20
- 3. Functional Architecture 27
- 3.1 Processor Sub-System 28
- 3.2 Memory Subsystem 29
- 3.2.1 Memory Supported 30
- 3.2.2 Post Error Codes 30
- 3.3 Intel 33
- Chipset PCH 33
- 3.4 I/O Sub-system 34
- 3.4.5 USB 2.0 Support 35
- 3.5 Optional Intel 36
- SAS RAID Module 36
- 3.6.3 Serial Ports 39
- 3.7 Video Support 40
- 3.7.2 Video for Intel 41
- Server Board S1200BTS 41
- 4. Platform Management 44
- 4.1 Feature Support 45
- 4.2.3 Media Redirection 50
- 4.2.4 Embedded Web server 51
- 4.3 Thermal Control 53
- 4.4 Intel 54
- 4.4.2 Features 55
- Server 58
- Board S1200BTS 58
- 6. BIOS User Interface 59
- 6.4 BIOS Boot Pop-up Menu 62
- 6.5 BIOS Setup Utility 62
- Table 16. Screen Map 66
- Frequency 74
- Hardware Prefetcher 74
- Adjacent Cache Line Prefetch 74
- 6.5.2.8 USB Configuration 84
- [40%/60%/80%/100%] 93
- Revision 1.0 102
- 7.2 Power Connectors 103
- 7.3.1 Intel 104
- RMM4) Lite connetor and 104
- Dedicated NIC connector 104
- 7.3.4 SGPIO Header 105
- 7.3.2 LPC/IPMB Header 105
- 7.3.3 HSBP Header 105
- 7.4.1 Power Button 106
- 7.4.2 Reset Button 107
- 7.5 I/O Connectors 108
- 7.5.3 SATA 109
- 7.5.4 SAS Connectors 109
- 7.5.6 USB Connector 111
- 7.7 Fan Headers 115
- 8. Jumper Blocks 116
- 8.1.1 Clearing the CMOS 118
- 8.1.2 Clearing the Password 118
- Server Board S1200BTL) 119
- 8.3 ME Force Update Jumper 119
- 8.4 BIOS Recovery Jumper 120
- 9. Intel 121
- Light Guided Diagnostics 121
- 10.1 Intel 123
- 10.3.1 Grounding 125
- 10.3.2 Standby Outputs 125
- 10.3.3 Remote Sense 125
- 10.3.4 Voltage Regulation 125
- 10.3.5 Dynamic Loading 125
- 10.3.6 Capacitive Loading 126
- 10.3.8 Common Mode Noise 126
- 10.3.9 Ripple/Noise 126
- 10.3.10 Timing Requirements 126
- 10.3.12 Protection Circuits 129
- Sensor Type Codes 132
- Table 56. BMC Core Sensors 134
- Appendix D: POST Code Errors 145
- POST Error Beep Codes 147
- Appendix E: Supported Intel 148
- Server Chassis 148
- Glossary 149
- Reference Documents 153
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