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Intel® Server Board S1200BT TPS Functional Architecture
Revision 1.0
Intel order number G13326-003
15
3. Functional Architecture
The architecture and design of the Intel
®
Server Board S1200BT is based on the Intel
®
C202
Chipset. The chipset is designed for systems based on the Intel
®
Xeon
®
processor in the FC-
LGA 1155 socket package.
The Intel
®
Server Board S1200BTL uses Intel
®
C204 Chipset and the Intel
®
Server Board
S1200BTS uses Intel
®
C202 Chipset.
The Intel
®
Xeon
®
Processor E3-1200 Series are made up of multi-core processors based on the
32nm processor technology. The Intel
®
Core™ Processor i3-2100 is made up of dual-core
processors based on the 32nm processor technology.
This chapter provides a high-level description of the functionality associated with each chipset
component and the architectural blocks that make up the server board.
PCIe Gen2 x4
x4 DMI Gen2
4
12
FLASHFLASH
LPC
Notes:
Dual GbE
RMII
SATA 3G
FLASHFLASH
BMC Boot
Flash
Intel
®
C204
Ch A Ch B
DDR3 (Channel B)
PCIe Gen2 x8
XDP
PCIe Gen1 x1
PCIe Gen2 x4
SPI
GLCI
USB 2.0
Slot 6
(PCIe Gen1 x1 in physical)
optional
on-board
4 Unbuffered
DIMMs
GbE
GbE
USB
1.1
USB
2.0
22
DDR3 (Channel A)
Lewisville
GbE
PHY
USB
RGMII
(x16 connector)
SERIAL 2
RMM4 Dedicated
NIC Module
2
2
SATA 6G
Mezzanine Module
GbE
Hartwell
2
USB
TPM
BIOS Flash
PCIe Gen1 x1
DDR3
PCIe Gen2 x4
PCIe Gen2 x4
Slot 5
Knoxvill
Socket H2
Intel
®
Xeon
®
Processor
E3-1200
Slot 4
(x8 connector)
(x8 connector)
Slot 3
PCI 32/33
(x8 connector)
Slot 1
Intel® Server Board S1200BTL Block Diagram
ATX - 12" x 9.6"
PCI
Internal USB
Header x2
I/O Module
Rear I/O USB
Ports x2
Type-A
Header
Zoar
SERIAL 1VIDEO
Rear I/O
VGA Port
Rear I/O
COM Port
Internal
Header
SATA-III
0
1
4
5
2
3
SATA-II
BMC
1. Video integrated into BMC.
A1 A0 B1 B0
SPI
SPI
RMM4 LITE
Module
Figure 11. Intel
®
Server Board S1200BTL Functional Block Diagram
- Server Board S1200BT 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 8
- List of Tables 10
- Revision 1.0 11
- 1. Introduction 13
- 2. Overview 14
- 2.2 Server Board Layout 16
- 2.2.2 Intel 20
- 3. Functional Architecture 27
- 3.1 Processor Sub-System 28
- 3.2 Memory Subsystem 29
- 3.2.1 Memory Supported 30
- 3.2.2 Post Error Codes 30
- 3.3 Intel 33
- Chipset PCH 33
- 3.4 I/O Sub-system 34
- 3.4.5 USB 2.0 Support 35
- 3.5 Optional Intel 36
- SAS RAID Module 36
- 3.6.3 Serial Ports 39
- 3.7 Video Support 40
- 3.7.2 Video for Intel 41
- Server Board S1200BTS 41
- 4. Platform Management 44
- 4.1 Feature Support 45
- 4.2.3 Media Redirection 50
- 4.2.4 Embedded Web server 51
- 4.3 Thermal Control 53
- 4.4 Intel 54
- 4.4.2 Features 55
- Server 58
- Board S1200BTS 58
- 6. BIOS User Interface 59
- 6.4 BIOS Boot Pop-up Menu 62
- 6.5 BIOS Setup Utility 62
- Table 16. Screen Map 66
- Frequency 74
- Hardware Prefetcher 74
- Adjacent Cache Line Prefetch 74
- 6.5.2.8 USB Configuration 84
- [40%/60%/80%/100%] 93
- Revision 1.0 102
- 7.2 Power Connectors 103
- 7.3.1 Intel 104
- RMM4) Lite connetor and 104
- Dedicated NIC connector 104
- 7.3.4 SGPIO Header 105
- 7.3.2 LPC/IPMB Header 105
- 7.3.3 HSBP Header 105
- 7.4.1 Power Button 106
- 7.4.2 Reset Button 107
- 7.5 I/O Connectors 108
- 7.5.3 SATA 109
- 7.5.4 SAS Connectors 109
- 7.5.6 USB Connector 111
- 7.7 Fan Headers 115
- 8. Jumper Blocks 116
- 8.1.1 Clearing the CMOS 118
- 8.1.2 Clearing the Password 118
- Server Board S1200BTL) 119
- 8.3 ME Force Update Jumper 119
- 8.4 BIOS Recovery Jumper 120
- 9. Intel 121
- Light Guided Diagnostics 121
- 10.1 Intel 123
- 10.3.1 Grounding 125
- 10.3.2 Standby Outputs 125
- 10.3.3 Remote Sense 125
- 10.3.4 Voltage Regulation 125
- 10.3.5 Dynamic Loading 125
- 10.3.6 Capacitive Loading 126
- 10.3.8 Common Mode Noise 126
- 10.3.9 Ripple/Noise 126
- 10.3.10 Timing Requirements 126
- 10.3.12 Protection Circuits 129
- Sensor Type Codes 132
- Table 56. BMC Core Sensors 134
- Appendix D: POST Code Errors 145
- POST Error Beep Codes 147
- Appendix E: Supported Intel 148
- Server Chassis 148
- Glossary 149
- Reference Documents 153
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