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Functional Architecture Intel® Server Board S1200BT TPS
Revision 1.0
Intel order number G13326-003
22
USB host interface
SMBus Host interface
Serial Peripheral interface
LAN interface
ACPI interface
3.4 I/O Sub-system
Intel
®
C200 Series PCH provides extensive I/O support.
3.4.1 Digital Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and C202
chipset. This high-speed interface integrates advanced priority-based servicing allowing for
concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current and legacy software to operate normally.
3.4.2 PCI Express Interface
The PCI-E configurations for each SKU are defined below:
Intel
®
Server Board S1200BTL
One PCI-E x16 connector to be used as a x8 link, two PCI-E x8 connectors to be used as a
x4 link and one SAS module connector to be used as a x4 link connected to the PCI-E
ports of the processor. One PCI-E x8 connector to be used as x4 link connected to the PC-
E ports of PCH.
Intel
®
Server Board S1200BTS
One PCI-E x16 connector to be used as x8 link, one PCI-E x8 connectors to be used as a
x8 link connected to the PCI-E ports of the processor. One PCI-E x8 connector to be used
as x4 link connected to the PCI-E ports of PCH.
There is one 32-bit, 33-MHz 5-V PCI slot, common on both SKUs.
Compatibility with the PCI addressing model is maintained to ensure all existing applications
and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-
Play specification. The initial recovered clock speed of 1.25 GHz results in 2.5 Gb/s each
direction, which provides a 250-MB/s communications channel in each direction (500 MB/s
total). This is close to twice the data rate of classic PCI. It is a fact that 8b/10b encoding is used
accounts for the 250 MB/s where quick calculations would imply 300 MB/s. The external
graphics ports support 5.0 GT/s speed as well. Operating at 5.0 GT/s results in twice as much
bandwidth per lane as compared to 2.5 GT/s operation.
When operating with two PCI Express* controllers, each controller can operate at either 2.5
GT/s or 5.0 GT/s. The PCI Express* architecture is specified in three layers: Transaction Layer,
Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries.
3.4.3 Serial ATA Support
The Intel
®
C200 Series chipset has two integrated SATA host controllers that support
independent DMA operation on up to six ports and supports data transfer rates of up to 6.0
Gb/s on up to two ports (Port 0 and 1 Only on S1200BTL) while all ports support rates up to 3.0
Gb/s. The SATA controller contains two modes of operation – a legacy mode using I/O space,
- Server Board S1200BT 1
- Revision History 2
- Disclaimers 3
- Table of Contents 4
- List of Figures 8
- List of Tables 10
- Revision 1.0 11
- 1. Introduction 13
- 2. Overview 14
- 2.2 Server Board Layout 16
- 2.2.2 Intel 20
- 3. Functional Architecture 27
- 3.1 Processor Sub-System 28
- 3.2 Memory Subsystem 29
- 3.2.1 Memory Supported 30
- 3.2.2 Post Error Codes 30
- 3.3 Intel 33
- Chipset PCH 33
- 3.4 I/O Sub-system 34
- 3.4.5 USB 2.0 Support 35
- 3.5 Optional Intel 36
- SAS RAID Module 36
- 3.6.3 Serial Ports 39
- 3.7 Video Support 40
- 3.7.2 Video for Intel 41
- Server Board S1200BTS 41
- 4. Platform Management 44
- 4.1 Feature Support 45
- 4.2.3 Media Redirection 50
- 4.2.4 Embedded Web server 51
- 4.3 Thermal Control 53
- 4.4 Intel 54
- 4.4.2 Features 55
- Server 58
- Board S1200BTS 58
- 6. BIOS User Interface 59
- 6.4 BIOS Boot Pop-up Menu 62
- 6.5 BIOS Setup Utility 62
- Table 16. Screen Map 66
- Frequency 74
- Hardware Prefetcher 74
- Adjacent Cache Line Prefetch 74
- 6.5.2.8 USB Configuration 84
- [40%/60%/80%/100%] 93
- Revision 1.0 102
- 7.2 Power Connectors 103
- 7.3.1 Intel 104
- RMM4) Lite connetor and 104
- Dedicated NIC connector 104
- 7.3.4 SGPIO Header 105
- 7.3.2 LPC/IPMB Header 105
- 7.3.3 HSBP Header 105
- 7.4.1 Power Button 106
- 7.4.2 Reset Button 107
- 7.5 I/O Connectors 108
- 7.5.3 SATA 109
- 7.5.4 SAS Connectors 109
- 7.5.6 USB Connector 111
- 7.7 Fan Headers 115
- 8. Jumper Blocks 116
- 8.1.1 Clearing the CMOS 118
- 8.1.2 Clearing the Password 118
- Server Board S1200BTL) 119
- 8.3 ME Force Update Jumper 119
- 8.4 BIOS Recovery Jumper 120
- 9. Intel 121
- Light Guided Diagnostics 121
- 10.1 Intel 123
- 10.3.1 Grounding 125
- 10.3.2 Standby Outputs 125
- 10.3.3 Remote Sense 125
- 10.3.4 Voltage Regulation 125
- 10.3.5 Dynamic Loading 125
- 10.3.6 Capacitive Loading 126
- 10.3.8 Common Mode Noise 126
- 10.3.9 Ripple/Noise 126
- 10.3.10 Timing Requirements 126
- 10.3.12 Protection Circuits 129
- Sensor Type Codes 132
- Table 56. BMC Core Sensors 134
- Appendix D: POST Code Errors 145
- POST Error Beep Codes 147
- Appendix E: Supported Intel 148
- Server Chassis 148
- Glossary 149
- Reference Documents 153
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