Intel B80532PG0962M Datasheet download pdf (Page 65)

Intel

Pentium

4 Processor on 0.13 Micron Process Datasheet 65

Pin Lists and Signal Descriptions

THERMTRIP# Output

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a level where permanent silicon damage may occur.

Measurement of the temperature is accomplished through an internal thermal

sensor which is configured to trip at approximately 135

°C. Upon assertion of

THERMTRIP#, the processor will shut off its internal clocks (thus halting program

execution) in an attempt to reduce the processor junction temperature. To protect

the processor, its core voltage (V

) must be removed within 0.5 seconds of the

assertion of THERMTRIP#.

For processors with CPUID of 0xF24:

• Once activated, THERMTRIP# remains latched until RESET# is asserted.

While the assertion of the RESET# signal will de-assert THERMTRIP#, if the

processor’s junction temperature remains at or above the trip level,

THERMTRIP# will again be asserted.

For processors with CPUID of 0xF27 and beyond:

• Driving of the THERMTRIP# signal is enabled within 10

µs of the assertion

of PWRGOOD and is disabled on de-assertion of PWRGOOD. Once

activated, THERMTRIP# remains latched until PWRGOOD is de-asserted.

While the de-assertion of the PWRGOOD signal will de-assert

THERMTRIP#, if the processor’s junction temperature remains at or above

the trip level, THERMTRIP# will again be asserted within 10

µs of the

assertion of PWRGOOD.

TMS Input

TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

TRDY# Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of all system bus agents.

TRST# Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven low during power on Reset. This can be done with a 680

Ω pull-down

resistor.

CCA

Input

CCA

provides isolated power for the internal processor core PLLs. Refer to the

appropriate Platform Design Guide for complete implementation details.

CCIOPLL

Input

CCIOPLL

provides isolated power for internal processor system bus PLLs. Follow

the guidelines for V

CCA

, and refer to the appropriate Platform Design Guide for

complete implementation details.

CC_SENSE

Output

CC_SENSE

is an isolated low impedance connection to processor core power

). It can be used to sense or measure power near the silicon with little noise.

VID Input

Independent 1.2 V supply must be routed to V

VID pin for the Pentium 4

processor on 0.13 micron process’s Voltage Identification circuit.

VID[4:0] Output

VID[4:0] (Voltage ID) pins are used to support automatic selection of power

supply voltages (V

). Unlike previous generations of processors, these are

open drain signals that are driven by the Pentium 4 processor on 0.13 micron

process and must be pulled up to 3.3 V (max.) with 1 k

Ω resistors. The voltage

supply for these pins must be valid before the VR can supply V

to the

processor. Conversely, the VR output must be disabled until the voltage supply

for the VID pins becomes valid. The VID pins are needed to support the

processor voltage specification variations. See Table 2-2 for definitions of these

pins. The VR must supply the voltage that is requested by the pins, or disable

itself.

SSA

Input V

SSA

is the isolated ground for internal PLLs.

SS_SENSE

Output

SS_SENSE

is an isolated low impedance connection to processor core V

. It

can be used to sense or measure ground near the silicon with little noise

Table 4-3. Signal Descriptions (Sheet 8 of 8)

Name Type Description

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 84 85

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