Intel CM8063701450500 Datasheet download pdf (Page 52)

Power Management

52 Datasheet, Volume 1

4.2.3 Requesting Low-Power Idle States

The primary software interfaces for requesting low power idle states are through the

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

However, software may make C-state requests using the legacy method of I/O reads

from the ACPI-defined processor clock control registers, referred to as P_LVLx. This

method of requesting C-states provides legacy support for operating systems that

initiate C-state transitions using I/O reads.

To seamless support of legacy operating systems, P_LVLx I/O reads are converted

within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads

do not directly result in I/O reads to the system. The feature, known as I/O MWAIT

redirection, must be enabled in the BIOS.

Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read

interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in

Table 4-9.

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict

the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any

P_LVLx reads outside of this range does not cause an I/O redirection to an MWAIT(Cx)-

like request. They fall through like a normal I/O instruction.

Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The

MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O

redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on

an interrupt even if interrupts are masked by EFLAGS.IF.

4.2.4 Core C-states

The following are general rules for all core C-states, unless specified otherwise:

• A core C-State is determined by the lowest numerical thread state (such as Thread

0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See

Table 4-7.

• A core transitions to C0 state when:

— An interrupt occurs

— There is an access to the monitored address if the state was entered using an

MWAIT instruction

• For core C1/C1E, core C3, and core C6, an interrupt directed toward a single thread

wakes only that thread. However, since both threads are no longer at the same

core C-state, the core resolves to C0.

• A system reset re-initializes all processor cores

4.2.4.1 Core C0 State

The normal operating state of a core where code is being executed.

Table 4-9. P_LVLx to MWAIT Conversion

P_LVLx MWAIT(Cx) Notes

P_LVL2 MWAIT(C3)

P_LVL3 MWAIT(C6) C6. No sub-states allowed.

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 111 112

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