Intel BX80623I72600K Datasheet download pdf (Page 22)

Interfaces

22 Datasheet, Volume 1

2.1.3.2.1 Dual-Channel Symmetric Mode

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum

performance on real world applications. Addresses are ping-ponged between the

channels after each cache line (64-byte boundary). If there are two requests, and the

second request is to an address on the opposite channel from the first, that request can

be sent before data from the first request has returned. If two consecutive cache lines

are requested, both may be retrieved simultaneously since they are ensured to be on

opposite channels. Use Dual-Channel Symmetric mode when both Channel A and

Channel B DIMM connectors are populated in any order, with the total amount of

memory in each channel being the same.

When both channels are populated with the same memory capacity and the boundary

between the dual channel zone and the single channel zone is the top of memory, IMC

operates completely in Dual-Channel Symmetric mode.

Note: The DRAM device technology and width may vary from one channel to the other.

2.1.4 Rules for Populating Memory Slots

In all modes, the frequency of system memory is the lowest frequency of all memory

modules placed in the system, as determined through the SPD registers on the

memory modules. The system memory controller supports one or two DIMM

connectors per channel. The usage of DIMM modules with different latencies is allowed,

but in that case, the worst latency (per channel) will be used. For dual-channel modes,

both channels must have a DIMM connector populated and for single-channel mode,

only a single-channel may have one or both DIMM connectors populated.

Note: In a 2 DIMM Per Channel (2DPC) daisy chain layout memory configuration, the furthest

DIMM from the processor of any given channel must always be populated first.

2.1.5 Technology Enhancements of Intel

Fast Memory Access

(Intel

FMA)

The following sections describe the Just-in-Time Scheduling, Command Overlap, and

Out-of-Order Scheduling Intel FMA technology enhancements.

2.1.5.1 Just-in-Time Command Scheduling

The memory controller has an advanced command scheduler where all pending

requests are examined simultaneously to determine the most efficient request to be

issued next. The most efficient request is picked from all pending requests and issued

to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,

instead of having all memory access requests go individually through an arbitration

mechanism forcing requests to be executed one at a time, they can be started without

interfering with the current request allowing for concurrent issuing of requests. This

allows for optimized bandwidth and reduced latency while maintaining appropriate

command spacing to meet system memory protocol.

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Intel BX80623I72600K Datasheet Page 22