Intel BX80623I72600K Datasheet download pdf (Page 20)

Interfaces

20 Datasheet, Volume 1

Notes:

1. System memory configurations are based on availability and are subject to change.

2. Interface does not support ULV/LV memory modulates or ULV/LV DIMMs.

2.1.2 System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and

command signal mode timings on the main memory interface:

•t

= CAS Latency

•t

RCD

= Activate Command to READ or WRITE Command delay

•t

= PRECHARGE Command Period

• CWL = CAS Write Latency

• Command Signal modes = 1n indicates a new command may be issued every clock

and 2n indicates a new command may be issued every 2 clocks. Command launch

mode programming depends on the transfer rate and memory configuration.

Notes:

1. System memory timing support is based on availability and is subject to change.

Table 2-2. Supported SO-DIMM Module Configurations (AIO Only)

1,2

Raw

Card

Version

DIMM

Capacity

DRAM Device

Technology

DRAM

Organization

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of

Row/Col

Address Bits

# of Banks

Inside

DRAM

Page Size

1 GB 1 Gb 64 M x 16 8 2 13/10 8 8K

2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K

1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K

2 GB 2 Gb 256 M x 8 8 1 15/10 8 8K

512 MB 1 Gb 64 M x 16 4 1 13/10 8 8K

1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K

2 GB 1 Gb 128 M x 8 16 2 14/10 8 8K

4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K

8 GB 4 Gb 512 M x 8 16 2 16/ 10 8 8K

Table 2-3. DDR3 System Memory Timing Support

Segment

Transfer

Rate

(MT/s)

tCL

(tCK)

tRCD

(tCK)

tRP

(tCK)

CWL

(tCK) DPC

CMD

Mode

Notes

All Desktop

segments

1066

7776

11n/2n

22n

8886

11n/2n

22n

1333 9 9 9 7

11n/2n

22n

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 109 110

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