Intel ARCHITECTURE IA-32 User Manual download pdf (Page 117)

100

101

General Optimization Guidelines 2

2-45

Aliasing Cases in the Pentium

4 and Intel

Xeon

Processors

Aliasing conditions that are specific to the Pentium 4 processor and Intel

Xeon processor are:

• 16K for code – there can only be one of these in the trace cache at a

time. If two traces whose starting addresses are 16K apart are in the

same working set, the symptom will be a high trace cache miss rate.

Solve this by offsetting one of the addresses by one or more bytes.

• Data conflict – can only have one instance of the data in the

first-level cache at a time. If a reference (load or store) occurs with

its linear address matching a data conflict condition with another

reference (load or store) which is under way, then the second

reference cannot begin until the first one is kicked out of the cache.

On Pentium 4 and Intel Xeon processors with CPUID signature of

family encoding 15, model encoding of 0, 1 or 2, the data conflict

condition applies to addresses having identical value in bits 15:6

(also referred to as 64K aliasing conflict). If you avoid this kind of

aliasing, you can speedup programs by a factor of three if they load

frequently from preceding stores with aliased addresses and there is

little other instruction-level parallelism available. The gain is

smaller when loads alias with other loads, which cause thrashing in

the first-level cache. On Pentium 4 and Intel Xeon processors with

CPUID signature of family encoding 15, model encoding 3, the

data conflict condition applies to addresses having identical value in

bits 21:6.

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