Intel ARCHITECTURE IA-32 User Manual download pdf (Page 402)

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IA-32 Intel® Architecture Optimization

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PackageID[ProcessorNUM] = PACKAGE_ID;

CoreID[ProcessorNum] = CORE_ID;

SmtID[ProcessorNum] = SMT_ID;

CacheID[ProcessorNUM] = CACHE_ID;

// Only the target cache is stored in this example

ProcessorNum++;

}

ThreadAffinityMask <<= 1;

}

NumStartedLPs = ProcessorNum;

CacheIDBucket is an array of unique Cache_ID values. Allocate an array

of NumStartedLPs count of entries in this array for the target cache level.

CacheProcessorMask is a corresponding array of the bit mask of logical

processors sharing the same target level cache, these are logical

processors with the same Cache_ID.

The algorithm below assumes there is symmetry across the modular

boundary of target cache topology if more than one socket is populated

in an MP system, and only the topology of the target cache level is discovered.

Topology of other cache level can be determined in a similar manner.

// Bucket Cache IDs and compute processor mask for the target cache of every package.

CacheNum = 1;

CacheIDBucket[0] = CacheID[0];

ProcessorMask = 1;

CacheProcessorMask[0] = ProcessorMask;

Example 7-13 Discovering the Affinity Masks for Sibling Logical Processors

Sharing the Same Cache (Contd.)

1 2 ... 397 398 399 400 401 402 403 404 405 406 407 ... 567 568

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