Intel DBS2400GP2 Datasheet download pdf (Page 57)

Intel

Server Board S2400GP TPS Functional Architecture

Revision 1.01

Intel order number G50295-002

 Eight I2C interfaces with master-slave and SMBus timeout support. All interfaces are

SMBus 2.0 compliant.

 Parallel general-purpose I/O Ports (16 direct, 32 shared)

 Serial general-purpose I/O Ports (80 in and 80 out)

 Three UARTs

 Platform Environmental Control Interface (PECI)

 Six general-purpose timers

 Interrupt controller

 Multiple SPI flash interfaces

 NAND/Memory interface

 Sixteen mailbox registers for communication between the BMC and host

 LPC ROM interface

 BMC watchdog timer capability

 SD/MMC card controller with DMA support

 LED support with programmable blink rate controls on GPIOs

 Port 80h snooping capability

 Secondary Service Processor (SSP), which provides the HW capability of off-loading

time critical processing tasks from the main ARM core.

3.12.1 Remote KVMS Support

 USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and

floppy

 USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse

 Hardware Based Video Compression and Redirection Logic

 Supports both text and Graphics redirection

 Hardware assisted Video redirection using the Frame Processing Engine

 Direct interface to the Integrated Graphics Controller registers and Frame buffer

 Hardware-based encryption engine

3.12.2 Integrated BMC Embedded LAN Channel

The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These

interfaces are not shared with the host system. At any time, only one dedicated interface may

be enabled for management traffic. The default active interface is the NIC 1 port.

For these channels, support can be enabled for IPMI-over-LAN and DHCP. For security reasons,

embedded LAN channels have the following default settings:

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Intel DBS2400GP2 Datasheet Page 57