Intel DBS2400GP2 Datasheet download pdf (Page 33)

Intel

Server Board S2400GP TPS Functional Architecture

Revision 1.01

Intel order number G50295-002

3.5 Intel

QuickPath Interconnect

The Intel

QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used

in the processor. The narrow high-speed links stitch together processors in distributed shared

memory and integrated I/O platform architecture. It offers much higher bandwidth with low

latency. The Intel

QuickPath Interconnect has an

efficient

architecture

allowing more

interconnect performance to be achieved in real systems. It has a snoop protocol optimized for

low latency and high scalability, as well as packet and lane structures enabling quick

completions of transactions. Reliability, availability, and serviceability features (RAS) are built into

the architecture.

The physical connectivity of each interconnect link is made up of twenty differential signal pairs

plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional

links to complete the connection between two components. This supports traffic in both

directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as

having five layers: Physical, Link, Routing, Transport, and Protocol.

The Intel

QuickPath Interconnect includes a cache coherency protocol to keep the distributed

memory and caching structures coherent during system operation. It supports both low-latency

source snooping and a scalable home snoop behavior. The coherency protocol provides for

direct cache-to-cache transfers for optimal latency.

3.6 Integrated Memory Controller (IMC) and Memory Subsystem

Integrated into the processor is a memory controller. Each processor provides three DDR3

channels that support the following:

 Unbuffered DDR3 and registered DDR3 DIMMs

 LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher

capacity memory subsystems

 Independent channel mode or lockstep mode

 Data burst length of eight cycles for all memory organization modes

 Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s

 64-bit wide channels plus 8-bits of ECC support for each channel

 DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V

 1Gb, 2Gb, and 4Gb DDR3 DRAM technologies supported for these devices:

o UDIMM DDR3 – SR x8 and x16 data widths, DR – x8 data width

o RDIMM DDR3 – SR,DR, and QR – x4 and x8 data widths

o LRDIMM DDR3 – QR – x4 and x8 data widths with direct map or with rank

multiplication

 Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM

 Open with adaptive idle page close timer or closed page policy

 Per channel memory test and initialization engine can initialize DRAM to all logical zeros

with valid ECC (with or without data scrambler) or a predefined test pattern

 Isochronous access support for Quality of Service (QoS)

 Minimum memory configuration: independent channel support with one DIMM populated

 Integrated dual SMBus* master controllers

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Intel DBS2400GP2 Datasheet Page 33

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