Intel E3 User Manual Page 103
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- Table of contents
- BOOKMARKS
- Processor E3-1200 v3 1
- Product Family 1
- 2 Order No.: 328907-001 2
- Contents 3
- Revision History 8
- 1.0 Introduction 9
- 1.1 Supported Technologies 10
- 1.2 Interfaces 11
- 1.3 Power Management Support 11
- 1.5 Package Support 12
- 1.6 Terminology 12
- 1.7 Related Documents 15
- 2.0 Interfaces 17
- 2.1.3.2 Intel 21
- Fast Memory Access (Intel 21
- FMA) Technology Enhancements 21
- 2.1.3.3 Data Scrambling 21
- 2.2 PCI Express* Interface 22
- 2.4 Processor Graphics 27
- Source Device Sink Device 32
- HDMI Source 33
- HDMI Sink 33
- 2.7 Intel 36
- <10pF/Node 37
- 3.0 Technologies 38
- 3.2 Intel 42
- Technology) 43
- 3.8 Intel 46
- 64 Architecture x2APIC 46
- Execute Disable Bit 47
- 4.0 Power Management 48
- States Supported 49
- Enhanced Intel 50
- SpeedStep 50
- Technology Key Features 50
- Thread 0 Thread 1 51
- Core 0 State 51
- Core N State 51
- Processor Package State 51
- C1 C1E C7C6C3 52
- 4.2.4 Core C-State Rules 53
- Package C-States 54
- 4.3.2.3 Dynamic Power-Down 60
- CCIO_TERM 61
- 5.0 Thermal Management 63
- Measure T 64
- (DTS) 2.0 66
- 5.4 Intel 67
- Thermal Specifications 67
- 5.5 Processor Temperature 69
- Adaptive Thermal Monitor 69
- THERMTRIP# Signal 72
- 5.8 Digital Thermal Sensor 73
- 5.9 Intel 74
- 5.9.2 Package Power Control 75
- 5.9.3 Turbo Time Parameter 75
- 6.0 Signal Description 77
- Table 24. Memory Channel B 78
- 6.8 Testability Signals 82
- 6.10 Power Sequencing 84
- 6.11 Processor Power Signals 84
- 6.12 Sense Pins 84
- 7.2 Power and Ground Lands 86
- Voltage Identification (VID) 86
- 7.5 Signal Groups 91
- DC Specifications 93
- 8.7 Processor Markings 103
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