Intel 80C186XL User Manual

80C186XL/80C188XLMicroprocessorUser’s Manual

ixCONTENTS11.3.1.4 Transcendental Instructions ...11-511.3.1.5 Constant Instru

3-19BUS INTERFACE UNITFigure 3-18. Normally Ready System TimingsConditions causing the BIU to become idle include the following.• The instruction pre

BUS INTERFACE UNIT3-20An idle bus state may or may not drive the bus. An idle bus state following a bus read cycle con-tinues to float the bus. An idl

3-21BUS INTERFACE UNITTOE, TACC and TCE define the maximum data access requirements for the memory device. Thesedevice parameters must be less than th

BUS INTERFACE UNIT3-223.5.1.1 Refresh Bus CyclesA refresh bus cycle operates similarly to a normal read bus cycle except for the following:• For a 16-

3-23BUS INTERFACE UNITFigure 3-21. Typical Write Bus CycleFigure 3-22 illustrates a typical 16-bit interface connection to a read/write device. Write

BUS INTERFACE UNIT3-24Most memory and peripheral devices latch data on the rising edge of the write strobe. Address,chip-select and data must be valid

3-25BUS INTERFACE UNITThe minimum device data hold time (from WR high) is defined by TDH. The calculated valuemust be greater than the minimum device

BUS INTERFACE UNIT3-26Figure 3-23. Interrupt Acknowledge Bus CycleT1 T2 T3 T4CLKOUTALETI TI T1 T2 T3AD15:0[AD7:0]RD, WRBHEDENDT/RLOCKS2:0INTA0INTA1

3-27BUS INTERFACE UNITFigure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminateboth bus cycles in the interrupt ac

BUS INTERFACE UNIT3-283.5.4 HALT Bus CycleSuspending the CPU reduces device power consumption and potentially reduces interrupt latencytime. The HLT i

CONTENTSxFIGURESFigure Page2-1 Simplified Functional Block Diagram of the 80C186 Family CPU ...2-22-2 Physical Address Ge

3-29BUS INTERFACE UNITFigure 3-25. HALT Bus Cycle Table 3-6. HALT Bus Cycle Pin StatesPin(s) Pin StateAD15:0 (AD7:0 for 8-bit) FloatA15:8 (8-bit) Dr

BUS INTERFACE UNIT3-303.5.5 Temporarily Exiting the HALT Bus StateA DMA request, refresh request or bus hold request causes the BIU to exit the HALT b

3-31BUS INTERFACE UNITFigure 3-27. Returning to HALT After a Refresh Bus CycleCLKOUTAD15:0[AD7:0]ALE [A15:8]A19:16AddressNote 1Note 2 Note 3NOTES:

BUS INTERFACE UNIT3-32Figure 3-28. Returning to HALT After a DMA Bus Cycle3.5.6 Exiting HALTAn NMI or any unmasked INTn interrupt causes the BIU to e

3-33BUS INTERFACE UNITFigure 3-29. Exiting HALT3.6 SYSTEM DESIGN ALTERNATIVESMost system designs require no signals other than those already provided

BUS INTERFACE UNIT3-343.6.1 Buffering the Data BusThe BIU generates two control signals, DEN and DT/R, to control bidirectional buffers or trans-ceive

3-35BUS INTERFACE UNITFigure 3-31. Buffered AD Bus SystemIn a fully buffered system, DEN directly drives the transceiver output enable. A partially b

BUS INTERFACE UNIT3-36Figure 3-32. Qualifying DEN with Chip-Selects 3.6.2 Synchronizing Software and Hardware EventsThe execution sequence of a progr

3-37BUS INTERFACE UNITThe WAIT instruction suspends program execution until one of two events occurs: an interruptis generated, or the TEST input pin

BUS INTERFACE UNIT3-38In general, prefix bytes (such as LOCK) are considered extensions of the instructions they pre-cede. Interrupts, DMA requests an

xiCONTENTSFIGURESFigure Page3-15 Generating a Normally Not-Ready Bus Signal ...3-163-16 Genera

3-39BUS INTERFACE UNITFigure 3-33. Queue Status Timing3.7 MULTI-MASTER BUS SYSTEM DESIGNSThe BIU supports protocols for transferring control of the l

BUS INTERFACE UNIT3-40Figure 3-34. Timing Sequence Entering HOLD3.7.1.1 HOLD Bus LatencyThe duration between the time that the external device assert

3-41BUS INTERFACE UNITThe major factors that influence bus latency are listed below (in order from longest delay to short-est delay).1. Bus Not Ready

BUS INTERFACE UNIT3-42Figure 3-35. Refresh Request During HOLDThe device requesting a bus hold must be able to detect a HLDA pulse that is one clock

3-43BUS INTERFACE UNITFigure 3-36. Latching HLDAThe removal of HOLD must be detected for at least one clock cycle to allow the BIU to regainthe bus a

BUS INTERFACE UNIT3-44Figure 3-37. Exiting HOLD 3.8 BUS CYCLE PRIORITIESThe BIU arbitrates requests for bus cycles from the Execution Unit, the inte

3-45BUS INTERFACE UNIT6. Internal error (e.g., divide error, overflow) interrupt vectoring sequence.7. Hardware (e.g., INT0, DMA) interrupt vectoring

4Peripheral Control Block

CONTENTSxiiFIGURESFigure Page6-11 Wait State and Ready Control Functions ...6-166-12 U

4-1CHAPTER 4PERIPHERAL CONTROL BLOCKAll integrated peripherals in the 80C186 Modular Core family are controlled by sets of registerswithin an integrat

PERIPHERAL CONTROL BLOCK4-2Figure 4-1. PCB Relocation RegisterRegister Name: PCB Relocation RegisterRegister Mnemonic: RELREGRegister Function: Reloc

4-3PERIPHERAL CONTROL BLOCK Table 4-1. Peripheral Control BlockPCB OffsetFunctionPCB OffsetFunctionPCB OffsetFunctionPCB OffsetFunction00H Reserved

PERIPHERAL CONTROL BLOCK4-44.3 RESERVED LOCATIONSMany locations within the Peripheral Control Block are not assigned to any peripheral. Unusedlocation

4-5PERIPHERAL CONTROL BLOCK4.4.3 F-Bus OperationThe F-Bus functions differently than the external data bus for byte and word accesses. All writetrans

PERIPHERAL CONTROL BLOCK4-64.4.3.1 Writing the PCB Relocation RegisterWhenever mapping the Peripheral Control Block to another location, the user shou

4-7PERIPHERAL CONTROL BLOCKAs an example, to relocate the Peripheral Control Block to the memory range 10000-100FFH, theuser would program the PCB Rel

5Clock Generation and Power Management

xiiiCONTENTSFIGURESFigure Page10-3 Source-Synchronized Transfers...10-51

5-1CHAPTER 5CLOCK GENERATION AND POWERMANAGEMENTThe clock generation and distribution circuits provide uniform clock signals for the ExecutionUnit, th

CLOCK GENERATION AND POWER MANAGEMENT5-25.1.1.1 Oscillator OperationA phase shift oscillator operates through positive feedback, where a non-inverted,

5-3CLOCK GENERATION AND POWER MANAGEMENTChoose C1 and L1 component values in the third overtone crystal circuit to satisfy the followingconditions:• T

CLOCK GENERATION AND POWER MANAGEMENT5-4To examine the parallel resonant frequency, refer to Figure 5-3(c), an equivalent circuit to Figure5-3(b). The

5-5CLOCK GENERATION AND POWER MANAGEMENT5.1.1.2 Selecting CrystalsWhen specifying crystals, consider these parameters:• Resonance and Load Capacitance

CLOCK GENERATION AND POWER MANAGEMENT5-6An important consideration when using crystals is that the oscillator start correctly over the volt-age and te

5-7CLOCK GENERATION AND POWER MANAGEMENTReset may be either cold (power-up) or warm. Figure 5-6 illustrates a cold reset. Assert the RESinput during p

CLOCK GENERATION AND POWER MANAGEMENT5-8Figure 5-6. Cold Reset WaveformRESAD15:0, S2:0RD, WR, DENDT/R, LOCKVccccVcc and X1 stable to RES high,appr

5-9CLOCK GENERATION AND POWER MANAGEMENTFigure 5-7. Warm Reset WaveformAt the second falling CLKOUT edge after sampling RES inactive, the processor d

CLOCK GENERATION AND POWER MANAGEMENT5-10Figure 5-8. Clock Synchronization at Reset5.2 POWER MANAGEMENTMany VLSI devices available today use dynamic

CONTENTSxivTABLESTable Page1-1 Comparison of 80C186 Modular Core Family Products...1-21-2 Related Document

5-11CLOCK GENERATION AND POWER MANAGEMENT5.2.1 Power-Save ModePower-Save mode is a means for reducing operating current. Power-Save mode enables a pro

CLOCK GENERATION AND POWER MANAGEMENT5-12Figure 5-9. Power-Save RegisterRegister Name: Power Save RegisterRegister Mnemonic: PWRSAVRegister Function:

5-13CLOCK GENERATION AND POWER MANAGEMENTFigure 5-10. Power-Save Clock Transition5.2.1.2 Leaving Power-Save ModePower-Save mode continues until one o

CLOCK GENERATION AND POWER MANAGEMENT5-14Example 5-1. Initializing the Power Management Unit for Power-Save Mode$mod186name example_PSU_code;FUNCTION

6Chip-Select Unit

6-1CHAPTER 6CHIP-SELECT UNITEvery system requires some form of component-selection mechanism to enable the CPU to ac-cess a specific memory or periphe

CHIP-SELECT UNIT6-2Figure 6-1. Common Chip-Select Generation Methods6.3 CHIP-SELECT UNIT FUNCTIONAL OVERVIEWThe Chip-Select Unit (CSU) decodes bus cy

6-3CHIP-SELECT UNITFigure 6-2. Chip-Select Block Diagram= Block Size UCS= Block Size LCSMCS3MCS2MCS1MCS0= Base Base + 0Base + 128Base + 256Base + 384

CHIP-SELECT UNIT6-4UCS Mapped only to the upper memory address space; selects the BOOT memorydevice (EPROM or Flash memory types).LCSMapped only to th

xvCONTENTSTABLESTable PageC-1 Instruction Format Variables...C-1C

6-5CHIP-SELECT UNITBy combining LCS, UCS and MCS3:0, you can cover up to 786 Kbytes of memory address space.Methods such as those shown in Figure 6-1

CHIP-SELECT UNIT6-66.4 PROGRAMMINGFour registers determine the operating characteristics of the chip-selects. The Peripheral ControlBlock defines the

6-7CHIP-SELECT UNITFigure 6-5. UMCS Register DefinitionRegister Name: UCS Control RegisterRegister Mnemonic: UMCSRegister Function: Controls the oper

CHIP-SELECT UNIT6-8Figure 6-6. LMCS Register DefinitionRegister Name: LCS Control RegisterRegister Mnemonic: LMCSRegister Function: Controls the oper

6-9CHIP-SELECT UNITFigure 6-7. MMCS Register DefinitionRegister Name: MCS Control RegisterRegister Mnemonic: MMCSRegister Function: Controls the oper

CHIP-SELECT UNIT6-10Figure 6-8. PACS Register DefinitionRegister Name: PCS Control RegisterRegister Mnemonic: PACSRegister Function: Controls the ope

6-11CHIP-SELECT UNITFigure 6-9. MPCS Register DefinitionRegister Name: MCS and PCS Alternate Control RegisterRegister Mnemonic: MPCSRegister Function

CHIP-SELECT UNIT6-12The UMCS and LMCS registers can be programmed in any sequence. To program the MCS andPCS chip-selects, follow this sequence:1. Pro

6-13CHIP-SELECT UNIT6.4.2.2 LCS Active RangeThe LCS starting address is fixed at zero in memory address space; its ending address is the pro-grammed b

CHIP-SELECT UNIT6-14Figure 6-10. MCS3:0 Active RangesTable 6-5. MCS Block Size and Start Address RestrictionsMPCS Block Size BitsBlock Size (Kbytes)

CONTENTSxviEXAMPLESExample Page5-1 Initializing the Power Management Unit for Power-Save Mode ...5-146-1 Initializing th

6-15CHIP-SELECT UNIT6.4.2.4 PCS Active RangeEach PCS chip-select starts at an offset above the base address programmed in the PACS registerand is acti

CHIP-SELECT UNIT6-16Figure 6-11. Wait State and Ready Control FunctionsThe R2 control bit determines whether the bus cycle completes normally (requir

6-17CHIP-SELECT UNITFor example, assume MCS3 overlaps UCS. MCS3 is programmed for two wait states and re-quires bus ready, while UCS is programmed for

CHIP-SELECT UNIT6-186.5 CHIP-SELECTS AND BUS HOLDThe Chip-Select Unit decodes only internally generated address and bus state information. An ex-terna

6-19CHIP-SELECT UNITFigure 6-13. Typical SystemLatchProcessorALEAD BusAddrBusPCS1DRQCEDRAM256KARDY20MCS3:0UCSPCS0LCSSRAM32KFloppyDiskCont

CHIP-SELECT UNIT6-20Example 6-1. Initializing the Chip-Select Unit$ TITLE (Chip-Select Unit Initialization)$ MOD186XREFNAME CSU_EXAMPLE_1; External

6-21CHIP-SELECT UNITExample 6-1. Initializing the Chip-Select Unit (Continued)DRAM_BASE EQU 256 ;window start address in KbytesDRAM_SIZE EQU 256 ;win

CHIP-SELECT UNIT6-22Example 6-1. Initializing the Chip-Select Unit (Continued)mov dx, MPCS_REG ;ready for PCS lines 4-6mov ax, MPCS_VAL ;as well as M

7Refresh Control Unit

1Introduction

7-1CHAPTER 7REFRESH CONTROL UNITThe Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrat-ed address and clock coun

REFRESH CONTROL UNIT7-27.1 THE ROLE OF THE REFRESH CONTROL UNITLike a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU exec

7-3REFRESH CONTROL UNITFigure 7-2. Refresh Control Unit Operation Flow ChartThe nine-bit refresh clock counter does not wait until the BIU services t

REFRESH CONTROL UNIT7-4The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates anotherrequest before the BIU handles the p

7-5REFRESH CONTROL UNIT7.5 REFRESH BUS CYCLESRefresh bus cycles look exactly like ordinary memory read bus cycles except for the control sig-nals list

REFRESH CONTROL UNIT7-6Figure 7-4. Suggested DRAM Control Signal Timing RelationshipsThe cycle begins with presentation of the row address. RAS shoul

7-7REFRESH CONTROL UNIT7.7 PROGRAMMING THE REFRESH CONTROL UNITGiven a specific processor operating frequency and information about the DRAMs in the s

REFRESH CONTROL UNIT7-87.7.2.1 Refresh Base Address RegisterThe Refresh Base Address Register (Figure 7-6) programs the base (upper seven bits) of the

7-9REFRESH CONTROL UNITFigure 7-7. Refresh Clock Interval Register7.7.2.3 Refresh Control RegisterFigure 7-8 shows the Refresh Control Register. The

REFRESH CONTROL UNIT7-10Figure 7-8. Refresh Control Register7.7.3 Programming ExampleExample 7-1 contains sample code to initialize the Refresh Contr

7-11REFRESH CONTROL UNITExample 7-1. Initializing the Refresh Control Unit$mod186name example_80C186_RCU_code; FUNCTION: This function initializes t

REFRESH CONTROL UNIT7-12Example 7-1. Initializing the Refresh Control Unit (Continued)7.8 REFRESH OPERATION AND BUS HOLDWhen another bus master contr

7-13REFRESH CONTROL UNITFigure 7-9. Regaining Bus Control to Run a DRAM Refresh Bus CycleHLDACLKOUTHOLDNOTES:1. HLDA is deasserted; signaling need

8Interrupt Control Unit

8-1CHAPTER 8INTERRUPT CONTROL UNITThe 80C186 Modular Core has a single maskable interrupt input. (See “Interrupts and ExceptionHandling” on page 2-39.

INTERRUPT CONTROL UNIT8-2Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requiresservicing. The CPU then stop

8-3INTERRUPT CONTROL UNIT8.2.1.1 Interrupt MaskingThere are circumstances in which a programmer may need to disable an interrupt source tempo-rarily (

INTERRUPT CONTROL UNIT8-4The priority of each source is programmable. The Interrupt Control register enables theprogrammer to assign each source a pri

80C186XL/80C188XLMicroprocessorUser’s Manual1995

1-1CHAPTER 1INTRODUCTIONThe 8086 microprocessor was first introduced in 1978 and gained rapid support as the microcom-puter engine of choice. There ar

8-5INTERRUPT CONTROL UNIT8.3 FUNCTIONAL OPERATION IN MASTER MODEThis section covers the process in which the Interrupt Control Unit receives interrupt

INTERRUPT CONTROL UNIT8-68.3.2.1 Priority Resolution ExampleThis example illustrates priority resolution. Assume these initial conditions:• the Interr

8-7INTERRUPT CONTROL UNIT8.3.2.2 Interrupts That Share a Single SourceMultiple interrupt requests can share a single interrupt input to the Interrupt

INTERRUPT CONTROL UNIT8-8Figure 8-2. Using External 8259A Modules in Cascade Mode8.3.3.1 Special Fully Nested ModeSpecial fully nested mode is an opt

8-9INTERRUPT CONTROL UNIT8.3.4 Interrupt Acknowledge SequenceDuring the interrupt acknowledge sequence, the Interrupt Control Unit passes the interrup

INTERRUPT CONTROL UNIT8-108.3.6 Edge and Level TriggeringThe external interrupts (INT3:0) can be programmed for either edge or level triggering (see “

8-11INTERRUPT CONTROL UNITFigure 8-3. Interrupt Control Unit Latency and Response Time8.4 PROGRAMMING THE INTERRUPT CONTROL UNITTable 8-3 lists the I

INTERRUPT CONTROL UNIT8-128.4.1 Interrupt Control Registers Each interrupt source has its own Interrupt Control register. The Interrupt Control regist

8-13INTERRUPT CONTROL UNITFigure 8-4. Interrupt Control Register for Internal SourcesRegister Name: Interrupt Control Register (internal sources)Regi

INTERRUPT CONTROL UNIT8-14.Figure 8-5. Interrupt Control Register for Noncascadable External PinsRegister Name: Interrupt Control Register (non-casca

INTRODUCTION1-2The 80C186 Modular Core family is the direct result of ten years of Intel development. It offersthe designer the peace of mind of a wel

8-15INTERRUPT CONTROL UNITFigure 8-6. Interrupt Control Register for Cascadable Interrupt PinsRegister Name: Interrupt Control Register (cascadable p

INTERRUPT CONTROL UNIT8-168.4.2 Interrupt Request RegisterThe Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a so

8-17INTERRUPT CONTROL UNITFigure 8-8. Interrupt Mask Register8.4.4 Priority Mask RegisterThe Priority Mask register (Figure 8-9) contains a three-lev

INTERRUPT CONTROL UNIT8-18Figure 8-9. Priority Mask Register8.4.5 In-Service RegisterThe In-Service register has a bit for each interrupt source. The

8-19INTERRUPT CONTROL UNITFigure 8-10. In-Service Register8.4.6 Poll and Poll Status RegistersThe Poll and Poll Status registers allow you to poll th

INTERRUPT CONTROL UNIT8-20Reading the Poll register (Figure 8-11) acknowledges the pending interrupt, just as if the CPUhad started the interrupt vect

8-21INTERRUPT CONTROL UNITFigure 8-12. Poll Status Register8.4.7 End-of-Interrupt (EOI) RegisterThe End-of-Interrupt register (Figure 8-13) issues an

INTERRUPT CONTROL UNIT8-22Figure 8-13. End-of-Interrupt Register8.4.8 Interrupt Status RegisterThe Interrupt Status register (Figure 8-14) contains t

8-23INTERRUPT CONTROL UNITFigure 8-14. Interrupt Status RegisterNOTEDo not write to the DHLT bit while Timer/Counter Unit interrupts are enabled. A c

INTERRUPT CONTROL UNIT8-24Figure 8-15. Interrupt Control Unit in Slave Mode8259A/82C59AINTINTACascadeAddressDecodeINT0INTASelect80186ModularCore

1-3INTRODUCTIONEach chapter covers a specific section of the device, beginning with the CPU core. Each periph-eral chapter includes programming exampl

8-25INTERRUPT CONTROL UNITFigure 8-16. Interrupt Sources in Slave Mode8.5.1 Slave Mode ProgrammingSome registers differ between Slave mode and Master

INTERRUPT CONTROL UNIT8-268.5.1.1 Interrupt Vector RegisterThe Interrupt Vector Register is used only in Slave mode. In Master mode, the interrupt vec

8-27INTERRUPT CONTROL UNITFigure 8-17. Interrupt Vector Register (Slave Mode Only)8.5.1.2 End-Of-Interrupt RegisterThe End-of-Interrupt (EOI) registe

INTERRUPT CONTROL UNIT8-28Figure 8-18. End-of-Interrupt Register in Slave Mode8.5.1.3 Other RegistersThe Priority Mask register is identical in Slave

8-29INTERRUPT CONTROL UNIT8.5.2 Interrupt Vectoring in Slave ModeIn Slave mode, the external 8259A module acts as the master interrupt controller. The

INTERRUPT CONTROL UNIT8-30External interrupt acknowledge cycles must be run for every maskable interrupt. Therefore, theinterrupt response time for ev

8-31INTERRUPT CONTROL UNIT5. Set the mask bit in the Interrupt Mask register for any interrupts that you wish to disable.Example 8-1 shows sample code

9Timer/Counter Unit

INTRODUCTION1-41.3 ELECTRONIC SUPPORT SYSTEMSIntel’s FaxBack* service and application BBS provide up-to-date technical information. Intelalso maintain

9-1CHAPTER 9TIMER/COUNTER UNITThe Timer/Counter Unit can be used in many applications. Some of these applications include areal-time clock, a square-w

TIMER/COUNTER UNIT9-2Figure 9-1. Timer/Counter Unit Block DiagramTransition Latch/SynchronizerTransition Latch/SynchronizerTimer 0RegistersTimer 1

9-3TIMER/COUNTER UNITFigure 9-2. Counter Element Multiplexing and Timer Input SynchronizationT1INT1OUTNOTES:1. T0IN resolution time (setup time met

TIMER/COUNTER UNIT9-4Figure 9-3. Timers 0 and 1 Flow ChartTimerEnabled(EN = 1)?Clear CountRegisterStartNoYesNoYesLo to Hitransition on inputpin

9-5TIMER/COUNTER UNITFigure 9-3. Timers 0 and 1 Flow Chart (Continued)No(Use"B")NoCounter = Compare "A"?AlternatingMaxcount R

TIMER/COUNTER UNIT9-6When configured for internal clocking, the Timer/Counter Unit uses the input pins either to en-able timer counting or to retrigge

9-7TIMER/COUNTER UNITFigure 9-5. Timer 0 and Timer 1 Control RegistersRegister Name: Timer 0 and 1 Control RegistersRegister Mnemonic: T0CON, T1CONRe

TIMER/COUNTER UNIT9-8Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)Register Name: Timer 0 and 1 Control RegistersRegister Mnemonic: T0

9-9TIMER/COUNTER UNITFigure 9-6. Timer 2 Control RegisterRegister Name: Timer 2 Control RegisterRegister Mnemonic: T2CONRegister Function: Defines Ti

TIMER/COUNTER UNIT9-10Figure 9-7. Timer Count RegistersRegister Name: Timer Count RegisterRegister Mnemonic: T0CNT, T1CNT, T2CNTRegister Function: Co

1-5INTRODUCTIONThe following catalogs and information are available at the time of publication:1. Solutions OEM subscription form2. Microcontroller an

9-11TIMER/COUNTER UNITFigure 9-8. Timer Maxcount Compare Registers9.2.1 Initialization SequenceWhen initializing the Timer/Counter Unit, the followin

TIMER/COUNTER UNIT9-129.2.2 Clock SourcesThe 16-bit Timer Count register increments once for each timer event. A timer event can be alow-to-high trans

9-13TIMER/COUNTER UNITThe timer counting from its initial count (usually zero) to its maximum count (either MaxcountCompare A or B) and resetting to z

TIMER/COUNTER UNIT9-14When the EXT bit is clear and the RTG bit is set, every low-to-high transition on the timer inputpin causes the Count register t

9-15TIMER/COUNTER UNITFigure 9-9. TxOUT Signal TimingIn dual maximum count mode, the timer output pin indicates which Maxcount Compare registeris cur

TIMER/COUNTER UNIT9-16The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timercounting. When using internal cloc

9-17TIMER/COUNTER UNIT9.3.2 Synchronization and Maximum FrequencyAll timer inputs are latched and synchronized with the CPU clock. Because of the inte

TIMER/COUNTER UNIT9-18Example 9-1. Configuring a Real-Time Clock$mod186name example_80186_family_timer_code;FUNCTION: This function sets up the timer

9-19TIMER/COUNTER UNITExample 9-1. Configuring a Real-Time Clock (Continued)lib_80186 segment public ’code’assume cs:lib_80186, ds:datapublic _set_ti

TIMER/COUNTER UNIT9-20Example 9-1. Configuring a Real-Time Clock (Continued)sti ;enable interruptspop si ;restore saved registerspop dxpop axpop bp ;

INTRODUCTION1-61.3.2.1 How to Find ApBUILDER Software and Hypertext Documents on the BBSThe latest ApBUILDER files and hypertext manuals and data shee

9-21TIMER/COUNTER UNITExample 9-2. Configuring a Square-Wave Generator$mod186name example_timer1_square_wave_code;FUNCTION: This function generates

TIMER/COUNTER UNIT9-22Example 9-2. Configuring a Square-Wave Generator (Continued)Example 9-3. Configuring a Digital One-Shotpop dx ;restore saved

9-23TIMER/COUNTER UNITExample 9-3. Configuring a Digital One-Shot (Continued)_CMPB equ word ptr[bp+6] ;get parameter off the stackpush ax ;save regi

10Direct Memory Access Unit

10-1CHAPTER 10DIRECT MEMORY ACCESS UNITIn many applications, large blocks of data must be transferred between memory and I/O space. Adisk drive, for e

DIRECT MEMORY ACCESS UNIT10-2When the DMA request is granted, the Bus Interface Unit provides the bus signals for the DMAtransfer, while the DMA chann

10-3DIRECT MEMORY ACCESS UNIT10.1.1.1 DMA Transfer DirectionsThe source and destination addresses for a DMA transfer are programmable and can be in ei

DIRECT MEMORY ACCESS UNIT10-410.1.4 External RequestsExternal DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the fallingedge o

1-7INTRODUCTION1.5 PRODUCT LITERATUREYou can order product literature from the following Intel literature centers. 1-800-468-8118, ext. 283 U.S. and C

10-5DIRECT MEMORY ACCESS UNIT10.1.4.1 Source SynchronizationA typical source-synchronized transfer is shown in Figure 10-3. Most DMA-driven peripheral

DIRECT MEMORY ACCESS UNIT10-6Figure 10-4. Destination-Synchronized Transfers10.1.5 Internal RequestsInternal DMA requests can come from either Timer

10-7DIRECT MEMORY ACCESS UNIT10.1.6 DMA Transfer CountsEach DMA Unit maintains a programmable 16-bit transfer count value that controls the totalnumbe

DIRECT MEMORY ACCESS UNIT10-810.1.8 DMA Unit InterruptsEach DMA channel can be programmed to generate an interrupt request when its transfer countreac

10-9DIRECT MEMORY ACCESS UNITThe last point is extremely important when the two channels use different synchronization. Forexample, consider the case

DIRECT MEMORY ACCESS UNIT10-10Figure 10-6. Examples of DMA Priority10.1.10.1.2 Rotating PriorityChannel priority rotates when the channels are progra

10-11DIRECT MEMORY ACCESS UNITTwo 16-bit Peripheral Control Block registers define each of the 20-bit pointers. Figures 10.7 and10.8 show the layout o

DIRECT MEMORY ACCESS UNIT10-12Figure 10-8. DMA Source Pointer (Low-Order Bits)The address space referenced by the source and destination pointers is

10-13DIRECT MEMORY ACCESS UNITFigure 10-9. DMA Destination Pointer (High-Order Bits)Register Name: DMA Destination Address Pointer (High)Register Mne

DIRECT MEMORY ACCESS UNIT10-14Figure 10-10. DMA Destination Pointer (Low-Order Bits)10.2.1.2 Selecting Byte or Word Size TransfersThe WORD bit in the

10-15DIRECT MEMORY ACCESS UNITFigure 10-11. DMA Control RegisterRegister Name: DMA Control RegisterRegister Mnemonic: DxCONRegister Function: Control

DIRECT MEMORY ACCESS UNIT10-16Figure 10-11. DMA Control Register (Continued)Register Name: DMA Control RegisterRegister Mnemonic: DxCONRegister Funct

10-17DIRECT MEMORY ACCESS UNITFigure 10-11. DMA Control Register (Continued)10.2.1.3 Selecting the Source of DMA RequestsDMA requests can come from e

DIRECT MEMORY ACCESS UNIT10-1810.2.1.4 Arming the DMA ChannelEach DMA channel must be armed before it can recognize DMA requests. A channel is armedby

10-19DIRECT MEMORY ACCESS UNITFigure 10-12. Transfer Count RegisterThe TC bit, when set, instructs the DMA channel to disarm itself (by clearing the

DIRECT MEMORY ACCESS UNIT10-2010.2.2 Suspension of DMA TransfersWhenever the CPU receives an NMI, all DMA activity is suspended at the end of the curr

10-21DIRECT MEMORY ACCESS UNIT10.3.2 DMA LatencyDMA Latency is the delay between a DMA request being asserted and the DMA cycle being run.The DMA late

DIRECT MEMORY ACCESS UNIT10-2210.3.4 Generating a DMA AcknowledgeThe DMA channels do not provide a distinct DMA acknowledge signal. A chip-select line

10-23DIRECT MEMORY ACCESS UNITExample 10-1. Initializing the DMA Unit$MOD186name DMA_EXAMPLE_1; This example shows code necessary to set up two DMA c

DIRECT MEMORY ACCESS UNIT10-24Example 10-1. Initializing the DMA Unit (Continued)MOV DX, D0DSTHMOV AX, BX ; GET HIGH NIBBLEOUT DX, AX; THE POINTER AD

2Overview of the 80C186 Family Architecture

10-25DIRECT MEMORY ACCESS UNITExample 10-1. Initializing the DMA Unit (Continued)MOV AX, 512 ; THE DISK READS IN 512 BYTE SECTORSMOV DX, D1TC ; XFER

DIRECT MEMORY ACCESS UNIT10-26Example 10-2. Timed DMA Transfers$mod186name DMA_EXAMPLE_1; This example sets up the DMA Unit to perform a transfer fro

10-27DIRECT MEMORY ACCESS UNITExample 10-2. Timed DMA Transfers (Continued); NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS:;; DESTINAT

11Math Coprocessing

11-1CHAPTER 11MATH COPROCESSINGThe 80C186 Modular Core Family meets the need for a general-purpose embedded microproces-sor. In most data control appl

MATH COPROCESSING11-2The core has an Escape Trap (ET) bit in the PCB Relocation Register (Figure 4-1 on page 4-2) tocontrol the availability of math c

11-3MATH COPROCESSING11.3.1.1 Data Transfer InstructionsData transfer instructions move operands between elements of the 80C187 register stack or be-t

MATH COPROCESSING11-4Available data types include temporary real, long real, short real, short integer and word integer.The 80C187 performs automatic

11-5MATH COPROCESSING11.3.1.3 Comparison InstructionsEach comparison instruction (see Table 11-3) analyzes the stack top element, often in relationshi

MATH COPROCESSING11-611.3.1.5 Constant InstructionsEach constant instruction (see Table 11-5) loads a commonly used constant onto the stack. Thevalues

11-7MATH COPROCESSING11.3.2 80C187 Data TypesThe microprocessor/math coprocessor combination supports seven data types:• Word Integer — A signed 16-bi

MATH COPROCESSING11-8Figure 11-1. 80C187-Supported Data TypesIncreasing SignificanceWordIntegerPackedDecimalShortRealTemporaryReal(Two's Complem

11-9MATH COPROCESSINGFigure 11-2. 80C186 Modular Core Family/80C187 System ConfigurationALEPEREQRESETPEREQ80C187CKMNPS280C186ModularCoreLatchD15:0E

MATH COPROCESSING11-1011.4.1 Clocking the 80C187The microprocessor and math coprocessor operate asynchronously, and their clock rates may dif-fer. The

11-11MATH COPROCESSINGBus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles withrespect to the processor’s control

MATH COPROCESSING11-12Figure 11-3. 80C187 Configuration with a Partially Buffered BusALEPEREQRESETPEREQEN80C187CKMNPS280C186ModularCore LatchD15:0E

11-13MATH COPROCESSING11.4.4 Exception TrappingThe 80C187 detects six error conditions that can occur during instruction execution. The 80C187can appl

MATH COPROCESSING11-14Figure 11-4. 80C187 Exception Trapping via Processor Interrupt PinINTxCLKOUTD15:0CMD1CMD0PEREQBUSYALEA19:A16AD15:0RESETCKMNPS2

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, includinginfringement of any p

2-1CHAPTER 2OVERVIEW OF THE 80C186 FAMILYARCHITECTUREThe 80C186 Modular Microprocessor Core shares a common base architecture with the 8086,8088, 8018

11-15MATH COPROCESSINGExample 11-1. Initialization Sequence for 80C187 Math Coprocessor$mod186name example_80C187_init;;FUNCTION: This function initi

MATH COPROCESSING11-16Example 11-2. Floating Point Math Routine Using FSINCOS$mod186$modc187name example_80C187_proc;DESCRIPTION: This code section u

12ONCE Mode

12-1CHAPTER 12ONCE MODEONCE (pronounced “ahnce”) Mode provides the ability to three-state all output, bidirectional, orweakly held high/low pins excep

ONCE MODE12-2Figure 12-1. Entering/Leaving ONCE ModeRESUCSLCSAll output,bidirectional,weakly heldpins exceptOSCOUTNOTES: 1. Entering ONCE Mode.2. Lat

A80C186 Instruction Set Additions and Extensions

A-1APPENDIX A80C186 INSTRUCTION SETADDITIONS AND EXTENSIONSThe 80C186 Modular Core family instruction set differs from the original 8086/8088 instruct

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA-2A.1.2 String InstructionsINS source_string, portINS (in string) performs block input from an I/O por

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-2Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU2.1.1 Execution UnitThe Executio

A-380C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSFigure A-1. Formal Definition of ENTERENTER treats a reentrant procedure as a procedure calling ano

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA-4Figure A-2. Variable Access in Nested ProceduresThe first ENTER, executed in the Main Program, allo

A-580C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSFigure A-4. Stack Frame for Procedure A at Level 2After Procedure A calls Procedure B, ENTER create

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA-6Figure A-5. Stack Frame for Procedure B at Level 3 Called from AA1004-0AOld BPBPSP15 0BPMBPMBPMDisp

A-780C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSFigure A-6. Stack Frame for Procedure C at Level 3 Called from BLEAVELEAVE reverses the action of t

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA-8BOUND register, addressBOUND verifies that the signed value in the specified register lies within sp

A-980C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA.2.2 Arithmetic InstructionsIMUL destination, source, dataIMUL (integer immediate multiply, signed)

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA-10A.2.3.2 Rotate InstructionsROL destination, countROL (immediate rotate left) rotates the destinatio

BInput Synchronization

2-3OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREThe Execution Unit does not connect directly to the system bus. It obtains instructions from aqueue maint

B-1APPENDIX BINPUT SYNCHRONIZATIONMany input signals to an embedded processor are asynchronous. Asynchronous signals do not re-quire a specified setup

INPUT SYNCHRONIZATIONB-2A synchronization failure can occur when the output of the first latch does not meet the setup andhold requirements of the inp

CInstruction Set Descriptions

C-1APPENDIX CINSTRUCTION SET DESCRIPTIONSThis appendix provides reference information for the 80C186 Modular Core family instructionset. Tables C-1 th

INSTRUCTION SET DESCRIPTIONSC-2Table C-2. Instruction OperandsOperand Descriptionreg An 8- or 16-bit general register.reg16 An 16-bit general registe

C-3INSTRUCTION SET DESCRIPTIONSTable C-3. Flag Bit FunctionsName FunctionAF Auxiliary Flag:Set on carry from or borrow to the low order four bits of

INSTRUCTION SET DESCRIPTIONSC-4Table C-4. Instruction Set Name Description OperationFlagsAffectedAAA ASCII Adjust for Addition:AAAChanges the content

C-5INSTRUCTION SET DESCRIPTIONSAAS ASCII Adjust for Subtraction:AASCorrects the result of a previous subtraction of two valid unpacked decimal operand

INSTRUCTION SET DESCRIPTIONSC-6ADD Addition:ADD dest, srcSums two operands, which may be bytes or words, replaces the destination operand. Both operan

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-4During periods when the Execution Unit is busy executing instructions, the Bus Interface Unitsequentially

C-7INSTRUCTION SET DESCRIPTIONSBOUND Detect Value Out of Range:BOUND dest, srcProvides array bounds checking in hardware. The calculated array index i

INSTRUCTION SET DESCRIPTIONSC-8CBW Convert Byte to Word:CBWExtends the sign of the byte in register AL throughout register AH. Use to produce a double

C-9INSTRUCTION SET DESCRIPTIONSCLI Clear Interrupt-enable Flag:CLIZeroes the interrupt-enable flag (IF). When the interrupt-enable flag is cleared, th

INSTRUCTION SET DESCRIPTIONSC-10CMP Compare:CMP dest, srcSubtracts the source from the desti-nation, which may be bytes or words, but does not return

C-11INSTRUCTION SET DESCRIPTIONSCWD Convert Word to Doubleword:CWDExtends the sign of the word in register AX throughout register DX. Use to produce a

INSTRUCTION SET DESCRIPTIONSC-12DEC Decrement:DEC destSubtracts one from the destination operand. The operand may be a byte or a word and is treated a

C-13INSTRUCTION SET DESCRIPTIONSDIV Divide:DIV srcPerforms an unsigned division of the accumulator (and its extension) by the source operand. If the s

INSTRUCTION SET DESCRIPTIONSC-14ENTER Procedure Entry:ENTER locals, levelsExecutes the calling sequence for a high-level language. It saves the curren

C-15INSTRUCTION SET DESCRIPTIONSHLT Halt:HLTCauses the CPU to enter the halt state. The processor leaves the halt state upon activation of the RESET l

INSTRUCTION SET DESCRIPTIONSC-16IDIV Integer Divide:IDIV srcPerforms a signed division of the accumulator (and its extension) by the source operand. I

2-5OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREThe data registers can be addressed by their upper or lower halves. Each data register can be usedinterch

C-17INSTRUCTION SET DESCRIPTIONSIMUL Integer Multiply:IMUL srcPerforms a signed multiplication of the source operand and the accumulator. If the sourc

INSTRUCTION SET DESCRIPTIONSC-18INC Increment:INC destAdds one to the destination operand. The operand may be byte or a word and is treated as an unsi

C-19INSTRUCTION SET DESCRIPTIONSINT Interrupt:INT interrupt-typeActivates the interrupt procedure specified by the interrupt-type operand. Decrements

INSTRUCTION SET DESCRIPTIONSC-20INTO Interrupt on Overflow:INTOGenerates a software interrupt if the overflow flag (OF) is set; otherwise control proc

C-21INSTRUCTION SET DESCRIPTIONSJAE JNBJump on Above or Equal:Jump on Not Below:JAE disp8JNB disp8Transfers control to the target location if the test

INSTRUCTION SET DESCRIPTIONSC-22JCXZ Jump if CX Zero:JCXZ disp8Transfers control to the target location if CX is 0. Useful at the beginning of a loop

C-23INSTRUCTION SET DESCRIPTIONSJLJNGEJump on Less Than:Jump on Not Greater Than or Equal:JL disp8JNGE disp8Transfers control to the target location i

INSTRUCTION SET DESCRIPTIONSC-24JNEJNZJump on Not Equal:Jump on Not Zero:JNE disp8JNZ disp8Transfers control to the target location if the tested cond

C-25INSTRUCTION SET DESCRIPTIONSJO Jump on Overflow:JO disp8Transfers control to the target location if the tested condition (OF = 1) is true.Instruct

INSTRUCTION SET DESCRIPTIONSC-26LDS Load Pointer Using DS:LDS dest, srcTransfers a 32-bit pointer variable from the source operand, which must be a me

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-6Figure 2-4. Segment Registers2.1.5 Instruction PointerThe Bus Interface Unit updates the 16-bit Instruct

C-27INSTRUCTION SET DESCRIPTIONSLES Load Pointer Using ES:LES dest, srcTransfers a 32-bit pointer variable from the source operand to the destination

INSTRUCTION SET DESCRIPTIONSC-28LODS Load String (Byte or Word):LODS src-stringTransfers the byte or word string element addressed by SI to register A

C-29INSTRUCTION SET DESCRIPTIONSLOOPNELOOPNZLoop While Not Equal:Loop While Not Zero:LOOPNE disp8LOOPNZ disp8Decrements CX by 1 and transfers control

INSTRUCTION SET DESCRIPTIONSC-30MOVS Move String:MOVS dest-string, src-stringTransfers a byte or a word from the source string (addressed by SI) to th

C-31INSTRUCTION SET DESCRIPTIONSNEG Negate:NEG destSubtracts the destination operand, which may be a byte or a word, from 0 and returns the result to

INSTRUCTION SET DESCRIPTIONSC-32OR Logical OR:OR dest,srcPerforms the logical "inclusive or" of the two operands (bytes or words) and return

C-33INSTRUCTION SET DESCRIPTIONSOUTS Out String:OUTS port, src_stringPerforms block output from memory to an I/O port. The port address is placed in t

INSTRUCTION SET DESCRIPTIONSC-34POPA Pop All:POPAPops all data, pointer, and index registers off of the stack. The SP value popped is discarded.Instru

C-35INSTRUCTION SET DESCRIPTIONSPUSHA Push All:PUSHAPushes all data, pointer, and index registers onto the stack . The order in which the registers ar

INSTRUCTION SET DESCRIPTIONSC-36RCL Rotate Through Carry Left:RCL dest, countRotates the bits in the byte or word destination operand to the left by t

2-7OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1.6 FlagsThe 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unitpo

C-37INSTRUCTION SET DESCRIPTIONSREPREPEREPZREPNEREPNZRepeat:Repeat While Equal:Repeat While Zero:Repeat While Not Equal:Repeat While Not Zero:Controls

INSTRUCTION SET DESCRIPTIONSC-38RET Return:RET optional-pop-valueTransfers control from a procedure back to the instruction following the CALL that ac

C-39INSTRUCTION SET DESCRIPTIONSROR Rotate Right:ROR dest, countOperates similar to ROL except that the bits in the destination byte or word are rotat

INSTRUCTION SET DESCRIPTIONSC-40SHLSALShift Logical Left:Shift Arithmetic Left:SHL dest, countSAL dest, countShifts the destination byte or word left

C-41INSTRUCTION SET DESCRIPTIONSSBB Subtract With Borrow:SBB dest, srcSubtracts the source from the desti-nation, subtracts one if CF is set, and retu

INSTRUCTION SET DESCRIPTIONSC-42SCAS Scan String:SCAS dest-stringSubtracts the destination string element (byte or word) addressed by DI from the cont

C-43INSTRUCTION SET DESCRIPTIONSSHR Shift Logical Right:SHR dest, srcShifts the bits in the destination operand (byte or word) to the right by the num

INSTRUCTION SET DESCRIPTIONSC-44STI Set Interrupt-enable Flag:STISets IF to 1, enabling processor recognition of maskable interrupt requests appearing

C-45INSTRUCTION SET DESCRIPTIONSSUB Subtract:SUB dest, srcThe source operand is subtracted from the destination operand, and the result replaces the d

INSTRUCTION SET DESCRIPTIONSC-46WAIT Wait:WAITCauses the CPU to enter the wait state while its test line is not active. Instruction Operands:noneNone

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-82.1.7 Memory SegmentationPrograms for the 80C186 Modular Core family view the 1 Mbyte memory space as a g

C-47INSTRUCTION SET DESCRIPTIONSXLAT Translate:XLAT translate-tableReplaces a byte in the AL register with a byte from a 256-byte, user-coded translat

DInstruction Set Opcodes and Clock Cycles

D-1APPENDIX DINSTRUCTION SET OPCODESAND CLOCK CYCLESThis appendix provides reference information for the 80C186 Modular Core family instructionset. Ta

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-2Table D-2. Instruction Set Summary Function Format Clocks NotesDATA TRANSFER INSTRUCTIONS MOV = Moveregist

D-3INSTRUCTION SET OPCODES AND CLOCK CYCLESDATA TRANSFER INSTRUCTIONS (Continued)LEA = Load EA to register 1 0 0 0 1 1 0 1 mod reg r/m 6LDS = Load poi

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-4ARITHMETIC INSTRUCTIONS (Continued)SUB = Subtractreg/memory with register to either0 0 1 0 1 0 d w mod reg

D-5INSTRUCTION SET OPCODES AND CLOCK CYCLESARITHMETIC INSTRUCTIONS (Continued)AAM = ASCII adjust for multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 19DIV =

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-6BIT MANIPULATION INSTRUCTIONS (Continued)TEST= And function to flags, no resultregister/memory and register

2-9OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-5. Processor Status WordRegister Name: Processor Status WordRegister Mnemonic: PSW (FLAGS)Regis

D-7INSTRUCTION SET OPCODES AND CLOCK CYCLESPROGRAM TRANSFER INSTRUCTIONSConditional Transfers — jump if:JE/JZ= equal/zero 0 1 1 1 0 1 0 0 disp 4/13 (2

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-8PROGRAM TRANSFER INSTRUCTIONS (Continued)RET = Return from procedurewithin segment1 1 0 0 0 0 1 1 16within

D-9INSTRUCTION SET OPCODES AND CLOCK CYCLESPROCESSOR CONTROL INSTRUCTIONSCLC = Clear carry 1 1 1 1 1 0 0 0 2CMC = Complement carry 1 1 1 1 0 1 0 1 2ST

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-1009 0000 1001 mod reg r/m (disp-lo),(disp-hi) or reg16/mem16,reg160A 0000 1010 mod reg r/m (disp-lo),(disp-

D-11INSTRUCTION SET OPCODES AND CLOCK CYCLES2E 0010 1110 DS: (segment override prefix)2F 0010 1111 das30 0011 0000 mod reg r/m (disp-lo),(disp-hi) xor

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-1253 0101 0011 push BX54 0101 0100 push SP55 0101 0101 push BP56 0101 0110 push SI57 0101 0111 push DI58 010

D-13INSTRUCTION SET OPCODES AND CLOCK CYCLES7E 0111 1110 IP-inc-8 jle/jng short-label7F 0111 1111 IP-inc-8 jnle/jg short-label80 1000 0000 mod 000 r

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-1487 1000 0111 mod reg r/m (disp-lo),(disp-hi) xchg reg16,reg16/mem1688 1000 0100 mod reg r/m (disp-lo),(di

D-15INSTRUCTION SET OPCODES AND CLOCK CYCLESAA 1010 1010 stos dest-str8AB 1010 1011 stos dest-str16AC 1010 1100 lods src-str8AD 1010 1101 lods src-str

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-16mod 111 r/m data-8 sar reg16/mem16, immed8C2 1100 0010 data-lo data-hi ret immed16 (intrasegment)C3 1100 0

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-10Figure 2-6. Segment Locations in Physical MemoryThe four segment registers point to four “currently add

D-17INSTRUCTION SET OPCODES AND CLOCK CYCLESD1 1101 0001 mod 000 r/m (disp-lo),(disp-hi) rol reg16/mem16,1mod 001 r/m (disp-lo),(disp-hi) ror reg16/me

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-18E1 1110 0001 IP-inc-8 loope/loopz short-labelE2 1110 0010 IP-inc-8 loop short-labelE3 1110 0011 IP-inc-8

D-19INSTRUCTION SET OPCODES AND CLOCK CYCLESF8 1111 1000 clcF9 1111 1001 stcFA 1111 1010 cliFB 1111 1011 stiFC 1111 1100 cldFD 1111 1101 stdFE 1111 11

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-20Table D-4. Mnemonic Encoding Matrix (Left Half)x0 x1 x2 x3 x4 x5 x6 x70xADDb,f,r/mADDw,f,r/mADDb,t,r/mADD

D-21INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-4. Mnemonic Encoding Matrix (Right Half)x8 x9 xA xB xC xD xE xFORb,f,r/mORw,f,r/mORb,t,r/mORw,t,r

INSTRUCTION SET OPCODES AND CLOCK CYCLESD-22Table D-5. Abbreviations for Mnemonic Encoding MatrixAbbr Definition Abbr Definition Abbr Definition Abbr

Index

Index-180C187 Math Coprocessor, 10-2–10-8accessing, 10-10–10-11arithmetic instructions, 10-3–10-4bus cycles, 10-11clocking, 10-10code examples,

INDEXIndex-2and chip-selects, 6-5HALT state, exiting, 3-30idle states, 3-18instruction prefetch, 3-20interrupt acknowledge (INTA) cycles, 3-6, 3-

iiiCONTENTSCHAPTER 1INTRODUCTION1.1 HOW TO USE THIS MANUAL... 1-21

2-11OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-7. Currently Addressable SegmentsThe segment register is automatically selected according to t

Index-3INDEXData sheets, obtaining from BBS, 1-5Data transfers, 3-1–3-6instructions, 2-18PCB considerations, 4-5PSW flag storage formats, 2-19See

INDEXIndex-4FFault exceptions, 2-43FaxBack service, 1-4F-Busand PCB, 4-5operation, 4-5Flags‚ See Processor Status Word (PSW)Floating Point, define

Index-5INDEXmaskable, 2-43masking, 8-3, 8-12, 8-16priority-based, 8-17multiplexed, 8-7nesting, 8-4NMI, 2-42nonmaskable, 2-45overview, 8-1, 8-2

INDEXIndex-6Polling, 8-1, 8-9POPA instruction, A-1Power consumption‚ reducing, 3-28Power management, 5-10–5-14Power management modesand HALT bus c

Index-7INDEXSI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32, 2-34Sign Flag (SF), 2-7, 2-9Single-step trap (Type 1 exception), 2-43Softwarecode

INDEXIndex-8and PCB accesses, 4-4and READY input, 3-13Word integer, defined, 10-7World Wide Web, 1-6Write bus cycle, 3-22ZZero Flag (ZF), 2-7, 2-

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-12Figure 2-8. Logical and Physical AddressPhysicalAddressSegmentBaseLogicalAddresses2C4H2C3H2C2H2C1H2C

2-13OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREInstructions are always fetched from the current code segment. The IP register contains the in-struction

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-14Figure 2-9. Dynamic Code RelocationTo be dynamically relocatable, a program must not load or alter its

2-15OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1.10 Stack ImplementationStacks in the 80C186 Modular Core family reside in memory space. They are loc

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-16Figure 2-10. Stack OperationA1013-0A10601062105E105B105A105810561054105210502200446688AA344589CD3311557

2-17OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2 SOFTWARE OVERVIEWAll 80C186 Modular Core family members execute the same instructions. This includes

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-182.2.1.1 Data Transfer InstructionsThe instruction set contains 14 data transfer instructions. These inst

2-19OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-11. Flag Storage Format2.2.1.2 Arithmetic InstructionsThe arithmetic instructions (see Table 2

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-20Table 2-5 shows the interpretations of various bit patterns according to number type. Binary num-bers ca

CONTENTSiv2.3 INTERRUPTS AND EXCEPTION HANDLING... 2-392.3.1 Interrupt/Exception Processing .

2-21OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.3 Bit Manipulation InstructionsThere are three groups of instructions for manipulating bits within

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-22Individual bits in bytes and words can also be rotated. The processor does not discard the bits ro-tated

2-23OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREString instructions automatically update the SI register, the DI register, or both, before processingthe

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-24Unconditional transfer instructions can transfer control either to a target instruction within thecurren

2-25OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-9. Program Transfer Instructions Conditional TransfersJA/JNBE Jump if above/not below nor equal

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-26Iteration control instructions can be used to regulate the repetition of software loops. These in-struct

2-27OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.6 Processor Control InstructionsProcessor control instructions (see Table 2-11) allow programs to

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-28Immediate operands are constant data contained in an instruction. Immediate data can be either8 or 16 bi

2-29OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-12. Memory Address ComputationThe displacement is an 8- or 16-bit number contained in the inst

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-30The BX or BP register can be specified as the base register for an effective address calculation.Similar

vCONTENTSCHAPTER 4PERIPHERAL CONTROL BLOCK4.1 PERIPHERAL CONTROL REGISTERS... 4-1

2-31OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-14. Register Indirect AddressingFigure 2-15. Based AddressingBased addressing provides a simp

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-32Figure 2-16. Accessing a Structure with Based AddressingWith indexed addressing, the effective address

2-33OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-17. Indexed AddressingFigure 2-18. Accessing an Array with Indexed AddressingEADISIOpcodeMod

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-34Based index addressing generates an effective address that is the sum of a base register, an indexregist

2-35OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-20. Accessing a Stacked Array with Based Index AddressingDisplacementEAHigh AddressIndex Regis

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-36Figure 2-21. String Operand 2.2.2.3 I/O Port AddressingAny memory operand addressing modes can be used

2-37OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.2.4 Data Types Used in the 80C186 Modular Core FamilyThe 80C186 Modular Core family supports the dat

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-38Figure 2-23. 80C186 Modular Core Family Supported Data Types 15+1870016+22324+331NOTE: *Directly suppo

2-39OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.3 INTERRUPTS AND EXCEPTION HANDLING Interrupts and exceptions alter program execution in response to

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-40Figure 2-25. Interrupt Vector TableWhen an interrupt is acknowledged, a common event sequence (Figure 2

CONTENTSvi6.4.5 Memory or I/O Bus Cycle Decoding ...6-176.4.6 Programming Conside

2-41OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2. The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. Thisprevents mas

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-42Figure 2-26. Interrupt Sequence2.3.1.1 Non-Maskable InterruptsThe Non-Maskable Interrupt (NMI) is the h

2-43OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.3.1.2 Maskable InterruptsMaskable interrupts are the most common way to service external hardware inte

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-44Breakpoint Interrupt — Type 3The Breakpoint Interrupt is a single-byte version of the INT instruction. I

2-45OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.3.2 Software InterruptsA Software Interrupt is caused by executing an “INTn” instruction. The n parame

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-462.3.4 Interrupt Response TimeInterrupt response time is the time from the CPU recognizing an interrupt u

2-47OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREOnly the single step exception can occur concurrently with another exception. At most, two ex-ceptions c

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2-48Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruc-tio

2-49OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-30. Simultaneous NMI, Single Step and Maskable Interrupt A1034-0ANMIPush PSW, CS, IPFetch Div

viiCONTENTS8.4 PROGRAMMING THE INTERRUPT CONTROL UNIT ... 8-118.4.1 Interrupt Control Registers ...

3Bus Interface Unit

3-1CHAPTER 3BUS INTERFACE UNITThe Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, passdata to and from the execu

BUS INTERFACE UNIT3-2Figure 3-1. Physical Data Bus ModelsByte transfers to even addresses transfer information over the lower half of the data bus (s

3-3BUS INTERFACE UNITFigure 3-2. 16-Bit Data Bus Byte TransfersEven Byte TransferOdd Byte TransferA19:1 D15:8 D7:0A0(Low) BHE(High)A19:1D15:8D7:0A0

BUS INTERFACE UNIT3-4Figure 3-3. 16-Bit Data Bus Even Word TransfersDuring a byte read operation, the BIU floats the entire 16-bit data bus, even tho

3-5BUS INTERFACE UNITFigure 3-4. 16-Bit Data Bus Odd Word Transfers3.2.2 8-Bit Data BusThe memory address space on an 8-bit data bus is physically im

BUS INTERFACE UNIT3-6For word transfers, the word address defines the first byte transferred. The second byte transferoccurs from the word address plu

3-7BUS INTERFACE UNIT3.3.1 16-Bit Bus Memory and I/O RequirementsA 16-bit bus has certain assumptions that must be met to operate properly. Memory use

BUS INTERFACE UNIT3-8Figure 3-6. Typical Bus CycleFigure 3-7. T-State Relation to CLKOUTFigure 3-8 shows the BIU state diagram. Typically a bus cycl

CONTENTSviii10.1.3 DMA Requests ...10-310.1.4 Ext

3-9BUS INTERFACE UNITThe address/status phase starts just before T1 and continues through T1. The data phase starts atT2 and continues through T4. Fig

BUS INTERFACE UNIT3-10Figure 3-9. T-State and Bus Phases3.4.1 Address/Status PhaseFigure 3-10 shows signal timing relationships for the address/statu

3-11BUS INTERFACE UNITFigure 3-10. Address/Status Phase Signal RelationshipsALEAD15:0A19:16CLKOUTS2:0BHET4or TIT1 T2142356ValidValidNOTES:1. TCHL

BUS INTERFACE UNIT3-12Figure 3-11. Demultiplexing Address InformationTable 3-1. Bus Cycle Types Status BitOperationS2 S1 S00 0 0 Interrupt Acknowled

3-13BUS INTERFACE UNIT3.4.2 Data PhaseFigure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycletype that does n

BUS INTERFACE UNIT3-14Figure 3-12. Data Phase Signal RelationshipsAD15:0WriteAD15:0ReadS2:0CLKOUTT2T3or TWT4or TIRD/ WR1423567ValidRead DataVali

3-15BUS INTERFACE UNITFigure 3-13. Typical Bus Cycle with Wait StatesFigure 3-14. ARDY and SRDY Pin Block DiagramALES2:0A19:16AD15:0READYWRCLKOUTT1

BUS INTERFACE UNIT3-16A normally not-ready system is one in which ARDY and SRDY remain low at all times exceptto signal a ready condition. For any bus

3-17BUS INTERFACE UNITFigure 3-16. Generating a Normally Ready Bus SignalThe ARDY input has two major timing concerns that can affect whether a norma

BUS INTERFACE UNIT3-18Figure 3-17. Normally Not-Ready System TimingA valid not-ready input can be generated as late as phase 1 of T3 to insert wait s