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Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
50 Order Number: 323103-001
2.1.7.1 Enabling SMI/NMI for Memory Corrected Errors
The MC_SMI_SPARE_CNTRL register has enables for SMI and NMI interrupts. Only one
should be set. Whichever type of interrupt is enabled will be triggered if:
• a DIMM error counter exceeds the threshold,
• redundancy is lost on a mirrored configuration, or
• a sparing operation completes.
This register is set by hardware once operation is complete. Bit is cleared by hardware
when a new operation is enabled. An SMI is generated when this bit is set due to a
sparing copy completion event.
Such an interrupt, once enabled by software, will be signaled only to the local
processor package where these events were detected. Therefore, the SMI/NMI
interrupt handler must be aware of the fact that the other processor package, if
present, did not receive the signalling of such SMI/NMI event.
2.1.7.2 Per DIMM Error Counters
There is one correctable ECC error counter for each DIMM that can be connected to the
Integrated Memory Controller. There are six MC_COR_ECC_CNT_X registers, each of
which holds a 15-bit counter and overflow bits for two DIMMs. The
Figure 9. Error Signaling Logic
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- Revision History 23
- 1.0 Features Summary 24
- Intel 3420 25
- Figure 2. Intel 26
- Configuration 26
- 1.2 Processor Feature Details 27
- 1.3 SKUs 27
- 1.4 Interfaces 28
- 1.4.3 PCI Express 29
- 1.4.6 SMBus 30
- 1.5 Power Management Support 31
- 1.7 Package 31
- 1.8 Terminology 32
- 1.9 Related Documents 33
- Table 4. PCH Documents 34
- 2.0 Interfaces 35
- 2.1.3.2 Single-Channel Mode 39
- 2.1.3.4 Spare Channel Mode 40
- 2.1.3.5 Mirrored Channel Mode 41
- 2.1.3.6 Lockstep Mode 42
- Channel 46
- Processor 47
- Fast Memory Access 48
- 2.1.5.2 Command Overlap 49
- 2.1.9 Patrol Scrub 51
- 2.1.10 Memory Address Decode 52
- 2.1.11 Address Translations 55
- 2.1.12 DDR Protocol Support 58
- 2.1.13 Refresh 58
- 2.1.14 Power Management 59
- . Since 63
- 2.1.14.8 2X Refresh 65
- 2.1.14.9 Demand Observation 66
- 2.1.14.10 Rank Sharing 67
- 2.1.14.11 Registers 67
- 2.2.1.1 Thermal Management 70
- 2.2.2.1 Ping() 71
- 2.2.2.2 GetDIB() 72
- 2.2.2.3 GetTemp() 73
- 2.2.2.4 PCIConfigRd() 74
- Reserved 75
- Bus Device Function Register 75
- 2.2.2.5 PCIConfigWr() 76
- 2.2.2.6 Mailbox 77
- 0 1 2 3 4 80
- Request Type Data[31:0] 80
- 2.2.2.7 MbxSend() 82
- 2.2.2.8 MbxGet() 84
- 2.2.3 Multi-Domain Commands 86
- 2.2.4.1 Abort FCS 87
- 2.2.4.2 Completion Codes 87
- 2.2.5 Originator Responses 88
- 2.2.6.1 Format 89
- 2.2.6.2 Interpretation 89
- 2.2.6.3 Temperature Filtering 89
- 2.2.6.4 Reserved Values 89
- 2.2.7.1 Power-up Sequencing 90
- 2.2.7.2 Device Discovery 91
- 2.2.7.3 Client Addressing 91
- 2.2.7.4 C-States 91
- 2.2.7.5 S-States 91
- 2.2.7.6 Processor Reset 92
- 2.3.2 Master SMBus 93
- 2.3.3 SMBus Physical Layer 93
- Address [15:8] 95
- Address [7:0] 95
- 2.3.7 SMBus Error Handling 97
- 2.3.8 SMBus Interface Reset 97
- 2.4 Intel 105
- 2.4.2.1 Processor’s Intel 107
- 2.4.3.1 Detect Intel 107
- Processors 107
- 2.4.5.1 Link Layer Attributes 108
- 2.4.9 Protocol Layer 109
- 2.4.7 Intel 109
- 2.4.8 Transport Layer 109
- 2.4.9.2 Intel 110
- 2.4.9.3 Intel 110
- 2.4.9.4 Interrupt Handling 110
- 2.4.9.5 Fault Handling 111
- 2.4.9.6 Reset/Initialization 111
- 2.4.9.7 Other Attributes 111
- 2.5.2.1 Link Error Protection 112
- 2.5.2.2 Message Class 112
- 2.5.2.4 Ordering 112
- 2.5.3 Protocol Layer 113
- 2.5.4 Snooping Modes 113
- 2.5.5.1 NodeID Generation 114
- 2.5.5.2 Memory Decoder 114
- 2.5.5.3 I/O Decoder 114
- 2.5.6 Special Response Status 115
- 2.5.8 Inbound Coherent 116
- 2.5.9 Inbound Non-Coherent 116
- 2.5.10 Profile Support 116
- 2.5.11.1 Write Cache Depth 117
- 2.5.11.2 Coherent Write Flow 117
- 2.5.11.3 Eviction Policy 117
- 2.5.13 Time-Out Counter 118
- 2.6 PCI Express Interface 119
- 2.6.1.1 Transaction Layer 120
- 2.6.1.2 Data Link Layer 120
- 2.6.1.3 Physical Layer 120
- 2.6.2.1 Link Training 120
- 2.6.2.2 Port Bifurcation 121
- 2.6.2.4 Degraded Mode 122
- 2.6.2.5 Lane Reversal 123
- 2.6.7 Inbound Transactions 125
- 2.6.8 Outbound Transactions 126
- 2.6.9 Lock Support 126
- 2.6.10.1 Unlock 127
- 2.6.10.2 EOI 127
- 2.6.12.1 Transaction ID 128
- 2.6.12.2 Attributes 129
- 2.6.12.3 Traffic Class 129
- 2.6.15 PCI Express RAS 130
- 2.6.16 ECRC Support 130
- 2.6.17 Completion Timeout 130
- 2.6.18 Data Poisoning 130
- 2.6.20.1 Ack/Nak 131
- 2.6.20.2 Link Level Retry 131
- 2.6.23.1 Polarity Inversion 133
- 2.7.1 DMI Error Flow 134
- 2.7.3 DMI Link Down 134
- 3.1 Introduction 135
- Processor 135
- C5500/C3500 Series 135
- Processor C5500/ 136
- C3500 Series NTB 136
- System A 139
- System B 139
- Root Complex 142
- 3.6 Architecture Overview 143
- Core Complex 144
- 3.6.3 Crosslink Configuration 146
- 3.6.6 Address Translation 152
- PCI EP captures Type 0 CFG 156
- WR Request and uses for 156
- 3.7 NTB Inbound Transactions 158
- 3.7.2.1 Error Reporting 159
- 3.8 Outbound Transactions 160
- 3.8.2 Lock Support 161
- 3.8.3.1 EOI 163
- 3.10.2 Attributes 164
- 3.11 Completer ID 165
- 3.12 Initialization 165
- 3.13 Reset Requirements 167
- 3.14 Power Management 167
- 3.16 MSI-X Vector Mapping 169
- 3.18.3 Bring Up Help 170
- PCI Header 171
- PCI Device 171
- Dependent 171
- Extended 171
- Configuration Space 171
- Bit Attr Default Description 175
- PCIE_ONLY 181
- Register default: 00003000h 193
- 3.19.4.9 HDRLOG: Header Log 211
- register exists 234
- Common Configuration Space 240
- E + 500h + Offset 241
- 1BASE + 500h + Offset 242
- Express NTB port 246
- MSICAPID 252
- MSINXTPTR 252
- MSIXCAPID 257
- MSIXNXTPTR 257
- MSIXMSGCTRL 257
- PBAOFF_BIR 259
- 3.21 NTB MMIO Space 277
- Table 94. NTB MMIO Map 278
- Table 95. NTB MMIO Map 300
- MSIXTBLn 301
- MSIXDATAn 301
- MSIXVECCNTLn 301
- Table 97. NTB MMIO Map 303
- 4.0 Technologies 306
- 4.1.2 Intel 307
- VT-x Features 307
- 4.1.3 Intel 307
- VT-d Objectives 307
- 4.2 Intel 308
- 4.2.1 Intel 309
- QuickData Technology 309
- 4.4 Intel 311
- Turbo Boost Technology 311
- 5.0 IIO Ordering Model 312
- 5.2 Inbound Ordering Rules 313
- 5.3 Outbound Ordering Rules 315
- 5.4.1 Hinted Peer-to-Peer 317
- 5.4.2 Local Peer-to-Peer 317
- 5.5 Interrupt Ordering Rules 318
- 5.7 Intel 319
- VT-d Ordering Exceptions 319
- 6.0 System Address Map 320
- 6.1 Memory Address Space 321
- 6.1.2.1 VGA/SMM Memory Space 323
- 6.1.2.2 C/D/E/F Segments 323
- 6.1.3.1 Relocatable TSeg 324
- 6.1.6.2 MMIOL 325
- 6.1.6.3 I/OxAPIC Memory Space 325
- 6.1.6.4 HPET/Others 326
- 6.1.6.5 Local XAPIC 326
- 6.1.6.6 Firmware 326
- 6.1.7.1 High System Memory 327
- 6.1.7.2 Memory Mapped IO High 327
- 6.2 IO Address Space 328
- 6.4.1.1 General Overview 329
- 6.4.1.2 FWH Decoding 331
- 6.4.1.3 I/OxAPIC Decoding 331
- IIO Behavior 334
- 6.4.2.1 Overview 335
- Peer-to-Peer (DP System) 336
- 6.4.3 Intel 338
- 7.0 Interrupts 339
- 7.2.1 Integrated I/OxAPIC 340
- into the remapping table 343
- 7.3.1 Interrupt Remapping 344
- 7.5 Platform Interrupts 347
- 7.6 Interrupt Flow 347
- 7.6.2 MSI Interrupt 348
- 8.0 Power Management 349
- 8.1.5 PCIe Link States 351
- Technology 353
- Processor Package State 354
- Core 1 State 354
- Core 0 State 354
- C1E C6C3 355
- 8.2.4.1 Core C0 State 356
- 8.2.4.2 Core C1E State 356
- 8.2.4.3 Core C3 State 357
- 8.2.4.4 Core C6 State 357
- 8.2.4.5 C-State Auto-Demotion 357
- 8.2.5.1 Package C0 359
- 8.2.5.2 Package C1E 359
- 8.2.5.3 Package C3 State 359
- 8.2.5.4 Package C6 State 360
- 8.4.2 Support for P-States 365
- 8.4.3 S0 -> S1 Transition 365
- 8.4.4 S1 -> S0 Transition 366
- 8.5 PCIe Power Management 367
- 8.6 DMI Power Management 367
- 8.7 Intel 368
- QPI Power Management 368
- 8.8 Intel 368
- 9.0 Thermal Management 369
- 10.0 Reset 370
- 10.2 Node ID Configuration 371
- 10.3 CPU-Only Reset 372
- 10.4 Reset Timing Diagrams 373
- 11.1 IIO RAS Overview 375
- 11.2 System Level RAS 376
- 11.3 IIO Error Reporting 376
- 11.3.2 Inband Error Reporting 378
- Per PCI- E Specification 382
- IIO Global 382
- Error Registers 382
- IIO Local 382
- Intel® QPI 1 384
- Intel® QPI 1-2 Error 384
- IIO ERROR 386
- REPORTING 386
- 11.3.3.6 Error Containment 390
- 11.3.3.7 Error Counters 391
- 11.3.3.8 Stop on Error 391
- 11.5 PCI Express* RAS 392
- 11.5.3.3 Error Forwarding 393
- 11.5.3.4 Unconnected Ports 393
- 11.7 Hot Add/Remove Support 408
- 11.7.1 Hot Add/Remove Rules 409
- 11.7.2 PCIe Hot Plug 409
- (P2P bridge, HPC) 410
- Slot 3 Slot 4 410
- Slot Control 412
- Regi ster 412
- Slot Status 412
- Regi st er 412
- Slot Status Register 413
- Slot Control Register 413
- Deassert 413
- 11.7.2.4 Operation 414
- 11.7.2.5 Miscellaneous Notes 416
- 11.7.3 Intel 417
- QPI Hot Plug 417
- 12.1 Signal Descriptions 418
- 12.1.3 PCI Express* Signals 422
- 12.1.5 DMI / ESI Signals 423
- 12.1.6 Clock Signals 423
- 12.1.8 Thermal Signals 424
- Table 147. Reset Signals 426
- 12.1.12 ITP Signals 427
- 13.1 Processor Signaling 483
- 13.1.4 PCI Express/DMI 484
- 13.1.5 SMBus Interface 485
- 13.1.6 Clock Signals 486
- 13.1.8 Thermal 486
- 13.1.10 Power / Other Signals 486
- 13.1.10.3 Processor V 487
- 13.1.10.4 Processor V 494
- 13.2 Signal Group Summary 495
- QuickPath Interconnect Input 496
- 13.3 Mixing Processors 500
- Table 163. V 505
- Example Overshoot Waveform 507
- 13.6.2 Die Voltage Validation 508
- 14.0 Testability 515
- Test-Logic 516
- PROCESSOR 518
- 14.4 TAP Port Timings 520
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